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authorFrancis Visoiu Mistrih <francisvm@yahoo.com>2017-11-30 12:12:19 +0000
committerFrancis Visoiu Mistrih <francisvm@yahoo.com>2017-11-30 12:12:19 +0000
commit7384652668585517500084ebf0c10e2946758f05 (patch)
tree657ad81ab9d251f7540f9b8bf75c5ee57b720622 /test/CodeGen/AArch64/tailcall_misched_graph.ll
parent996d6ddb49d9353fce795894a7be554f69f3e3ed (diff)
[CodeGen] Print "%vreg0" as "%0" in both MIR and debug output
As part of the unification of the debug format and the MIR format, avoid printing "vreg" for virtual registers (which is one of the current MIR possibilities). Basically: * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/%vreg([0-9]+)/%\1/g" * grep -nr '%vreg' . and fix if needed * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/ vreg([0-9]+)/ %\1/g" * grep -nr 'vreg[0-9]\+' . and fix if needed Differential Revision: https://reviews.llvm.org/D40420 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319427 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/AArch64/tailcall_misched_graph.ll')
-rw-r--r--test/CodeGen/AArch64/tailcall_misched_graph.ll10
1 files changed, 5 insertions, 5 deletions
diff --git a/test/CodeGen/AArch64/tailcall_misched_graph.ll b/test/CodeGen/AArch64/tailcall_misched_graph.ll
index 7e76dac214a..cb42fcced8d 100644
--- a/test/CodeGen/AArch64/tailcall_misched_graph.ll
+++ b/test/CodeGen/AArch64/tailcall_misched_graph.ll
@@ -26,9 +26,9 @@ declare void @callee2(i8*, i8*, i8*, i8*, i8*,
; CHECK: fi#-2: {{.*}} fixed, at location [SP+8]
; CHECK: fi#-1: {{.*}} fixed, at location [SP]
-; CHECK: [[VRA:%vreg.*]]<def> = LDRXui <fi#-1>
-; CHECK: [[VRB:%vreg.*]]<def> = LDRXui <fi#-2>
-; CHECK: STRXui %vreg{{.*}}, <fi#-4>
+; CHECK: [[VRA:%.*]]<def> = LDRXui <fi#-1>
+; CHECK: [[VRB:%.*]]<def> = LDRXui <fi#-2>
+; CHECK: STRXui %{{.*}}, <fi#-4>
; CHECK: STRXui [[VRB]], <fi#-3>
; Make sure that there is an dependence edge between fi#-2 and fi#-4.
@@ -40,5 +40,5 @@ declare void @callee2(i8*, i8*, i8*, i8*, i8*,
; CHECK: SU([[DEPSTOREB:.*]]): Ord Latency=0
; CHECK: SU([[DEPSTOREA:.*]]): Ord Latency=0
-; CHECK: SU([[DEPSTOREA]]): STRXui %vreg{{.*}}, <fi#-4>
-; CHECK: SU([[DEPSTOREB]]): STRXui %vreg{{.*}}, <fi#-3>
+; CHECK: SU([[DEPSTOREA]]): STRXui %{{.*}}, <fi#-4>
+; CHECK: SU([[DEPSTOREB]]): STRXui %{{.*}}, <fi#-3>