[CodeGen] Print "%vreg0" as "%0" in both MIR and debug output

As part of the unification of the debug format and the MIR format, avoid
printing "vreg" for virtual registers (which is one of the current MIR
possibilities).

Basically:

* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/%vreg([0-9]+)/%\1/g"
* grep -nr '%vreg' . and fix if needed
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/ vreg([0-9]+)/ %\1/g"
* grep -nr 'vreg[0-9]\+' . and fix if needed

Differential Revision: https://reviews.llvm.org/D40420

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319427 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 26 insertions, 26 deletions

diff --git a/test/CodeGen/AArch64/arm64-ldp-cluster.ll b/test/CodeGen/AArch64/arm64-ldp-cluster.ll
index 64e535ca749..ca50e110a88 100644
--- a/test/CodeGen/AArch64/arm64-ldp-cluster.ll
+++ b/test/CodeGen/AArch64/arm64-ldp-cluster.ll
@@ -6,13 +6,13 @@
 ; CHECK: ********** MI Scheduling **********
 ; CHECK-LABEL: ldr_int:BB#0
 ; CHECK: Cluster ld/st SU(1) - SU(2)
-; CHECK: SU(1):   %vreg{{[0-9]+}}<def> = LDRWui
-; CHECK: SU(2):   %vreg{{[0-9]+}}<def> = LDRWui
+; CHECK: SU(1):   %{{[0-9]+}}<def> = LDRWui
+; CHECK: SU(2):   %{{[0-9]+}}<def> = LDRWui
 ; EXYNOS: ********** MI Scheduling **********
 ; EXYNOS-LABEL: ldr_int:BB#0
 ; EXYNOS: Cluster ld/st SU(1) - SU(2)
-; EXYNOS: SU(1):   %vreg{{[0-9]+}}<def> = LDRWui
-; EXYNOS: SU(2):   %vreg{{[0-9]+}}<def> = LDRWui
+; EXYNOS: SU(1):   %{{[0-9]+}}<def> = LDRWui
+; EXYNOS: SU(2):   %{{[0-9]+}}<def> = LDRWui
 define i32 @ldr_int(i32* %a) nounwind {
   %p1 = getelementptr inbounds i32, i32* %a, i32 1
   %tmp1 = load i32, i32* %p1, align 2
@@ -26,13 +26,13 @@ define i32 @ldr_int(i32* %a) nounwind {
 ; CHECK: ********** MI Scheduling **********
 ; CHECK-LABEL: ldp_sext_int:BB#0
 ; CHECK: Cluster ld/st SU(1) - SU(2)
-; CHECK: SU(1):   %vreg{{[0-9]+}}<def> = LDRSWui
-; CHECK: SU(2):   %vreg{{[0-9]+}}<def> = LDRSWui
+; CHECK: SU(1):   %{{[0-9]+}}<def> = LDRSWui
+; CHECK: SU(2):   %{{[0-9]+}}<def> = LDRSWui
 ; EXYNOS: ********** MI Scheduling **********
 ; EXYNOS-LABEL: ldp_sext_int:BB#0
 ; EXYNOS: Cluster ld/st SU(1) - SU(2)
-; EXYNOS: SU(1):   %vreg{{[0-9]+}}<def> = LDRSWui
-; EXYNOS: SU(2):   %vreg{{[0-9]+}}<def> = LDRSWui
+; EXYNOS: SU(1):   %{{[0-9]+}}<def> = LDRSWui
+; EXYNOS: SU(2):   %{{[0-9]+}}<def> = LDRSWui
 define i64 @ldp_sext_int(i32* %p) nounwind {
   %tmp = load i32, i32* %p, align 4
   %add.ptr = getelementptr inbounds i32, i32* %p, i64 1
@@ -47,13 +47,13 @@ define i64 @ldp_sext_int(i32* %p) nounwind {
 ; CHECK: ********** MI Scheduling **********
 ; CHECK-LABEL: ldur_int:BB#0
 ; CHECK: Cluster ld/st SU(2) - SU(1)
-; CHECK: SU(1):   %vreg{{[0-9]+}}<def> = LDURWi
-; CHECK: SU(2):   %vreg{{[0-9]+}}<def> = LDURWi
+; CHECK: SU(1):   %{{[0-9]+}}<def> = LDURWi
+; CHECK: SU(2):   %{{[0-9]+}}<def> = LDURWi
 ; EXYNOS: ********** MI Scheduling **********
 ; EXYNOS-LABEL: ldur_int:BB#0
 ; EXYNOS: Cluster ld/st SU(2) - SU(1)
-; EXYNOS: SU(1):   %vreg{{[0-9]+}}<def> = LDURWi
-; EXYNOS: SU(2):   %vreg{{[0-9]+}}<def> = LDURWi
+; EXYNOS: SU(1):   %{{[0-9]+}}<def> = LDURWi
+; EXYNOS: SU(2):   %{{[0-9]+}}<def> = LDURWi
 define i32 @ldur_int(i32* %a) nounwind {
   %p1 = getelementptr inbounds i32, i32* %a, i32 -1
   %tmp1 = load i32, i32* %p1, align 2
@@ -67,13 +67,13 @@ define i32 @ldur_int(i32* %a) nounwind {
 ; CHECK: ********** MI Scheduling **********
 ; CHECK-LABEL: ldp_half_sext_zext_int:BB#0
 ; CHECK: Cluster ld/st SU(3) - SU(4)
-; CHECK: SU(3):   %vreg{{[0-9]+}}<def> = LDRSWui
-; CHECK: SU(4):   %vreg{{[0-9]+}}:sub_32<def,read-undef> = LDRWui
+; CHECK: SU(3):   %{{[0-9]+}}<def> = LDRSWui
+; CHECK: SU(4):   %{{[0-9]+}}:sub_32<def,read-undef> = LDRWui
 ; EXYNOS: ********** MI Scheduling **********
 ; EXYNOS-LABEL: ldp_half_sext_zext_int:BB#0
 ; EXYNOS: Cluster ld/st SU(3) - SU(4)
-; EXYNOS: SU(3):   %vreg{{[0-9]+}}<def> = LDRSWui
-; EXYNOS: SU(4):   %vreg{{[0-9]+}}:sub_32<def,read-undef> = LDRWui
+; EXYNOS: SU(3):   %{{[0-9]+}}<def> = LDRSWui
+; EXYNOS: SU(4):   %{{[0-9]+}}:sub_32<def,read-undef> = LDRWui
 define i64 @ldp_half_sext_zext_int(i64* %q, i32* %p) nounwind {
   %tmp0 = load i64, i64* %q, align 4
   %tmp = load i32, i32* %p, align 4
@@ -90,13 +90,13 @@ define i64 @ldp_half_sext_zext_int(i64* %q, i32* %p) nounwind {
 ; CHECK: ********** MI Scheduling **********
 ; CHECK-LABEL: ldp_half_zext_sext_int:BB#0
 ; CHECK: Cluster ld/st SU(3) - SU(4)
-; CHECK: SU(3):   %vreg{{[0-9]+}}:sub_32<def,read-undef> = LDRWui
-; CHECK: SU(4):   %vreg{{[0-9]+}}<def> = LDRSWui
+; CHECK: SU(3):   %{{[0-9]+}}:sub_32<def,read-undef> = LDRWui
+; CHECK: SU(4):   %{{[0-9]+}}<def> = LDRSWui
 ; EXYNOS: ********** MI Scheduling **********
 ; EXYNOS-LABEL: ldp_half_zext_sext_int:BB#0
 ; EXYNOS: Cluster ld/st SU(3) - SU(4)
-; EXYNOS: SU(3):   %vreg{{[0-9]+}}:sub_32<def,read-undef> = LDRWui
-; EXYNOS: SU(4):   %vreg{{[0-9]+}}<def> = LDRSWui
+; EXYNOS: SU(3):   %{{[0-9]+}}:sub_32<def,read-undef> = LDRWui
+; EXYNOS: SU(4):   %{{[0-9]+}}<def> = LDRSWui
 define i64 @ldp_half_zext_sext_int(i64* %q, i32* %p) nounwind {
   %tmp0 = load i64, i64* %q, align 4
   %tmp = load i32, i32* %p, align 4
@@ -113,13 +113,13 @@ define i64 @ldp_half_zext_sext_int(i64* %q, i32* %p) nounwind {
 ; CHECK: ********** MI Scheduling **********
 ; CHECK-LABEL: ldr_int_volatile:BB#0
 ; CHECK-NOT: Cluster ld/st
-; CHECK: SU(1):   %vreg{{[0-9]+}}<def> = LDRWui
-; CHECK: SU(2):   %vreg{{[0-9]+}}<def> = LDRWui
+; CHECK: SU(1):   %{{[0-9]+}}<def> = LDRWui
+; CHECK: SU(2):   %{{[0-9]+}}<def> = LDRWui
 ; EXYNOS: ********** MI Scheduling **********
 ; EXYNOS-LABEL: ldr_int_volatile:BB#0
 ; EXYNOS-NOT: Cluster ld/st
-; EXYNOS: SU(1):   %vreg{{[0-9]+}}<def> = LDRWui
-; EXYNOS: SU(2):   %vreg{{[0-9]+}}<def> = LDRWui
+; EXYNOS: SU(1):   %{{[0-9]+}}<def> = LDRWui
+; EXYNOS: SU(2):   %{{[0-9]+}}<def> = LDRWui
 define i32 @ldr_int_volatile(i32* %a) nounwind {
   %p1 = getelementptr inbounds i32, i32* %a, i32 1
   %tmp1 = load volatile i32, i32* %p1, align 2
@@ -133,8 +133,8 @@ define i32 @ldr_int_volatile(i32* %a) nounwind {
 ; CHECK: ********** MI Scheduling **********
 ; CHECK-LABEL: ldq_cluster:BB#0
 ; CHECK: Cluster ld/st SU(1) - SU(3)
-; CHECK: SU(1):   %vreg{{[0-9]+}}<def> = LDRQui
-; CHECK: SU(3):   %vreg{{[0-9]+}}<def> = LDRQui
+; CHECK: SU(1):   %{{[0-9]+}}<def> = LDRQui
+; CHECK: SU(3):   %{{[0-9]+}}<def> = LDRQui
 ; EXYNOS: ********** MI Scheduling **********
 ; EXYNOS-LABEL: ldq_cluster:BB#0
 ; EXYNOS-NOT: Cluster ld/st