diff options
| author | Sander de Smalen <sander.desmalen@arm.com> | 2017-12-18 11:29:59 +0000 |
|---|---|---|
| committer | Sander de Smalen <sander.desmalen@arm.com> | 2017-12-18 11:29:59 +0000 |
| commit | 9d49216adefc265699dd9e1b88f8b963afeae3a2 (patch) | |
| tree | 4f7cacdefa27e49b44369ae81a91a117ef8810cc /lib | |
| parent | 29dd081e8dbacdfdcedd10691419ed0d95e820fb (diff) | |
[AArch64][SVE] Asm: Add ZIP1/ZIP2 instructions (predicate/data vectors)
Summary: Patch [2/4] in a series to add parsing of predicates and properly parse SVE ZIP1/ZIP2 instructions.
Reviewers: rengolin, kristof.beyls, fhahn, mcrosier, evandro
Reviewed By: fhahn
Subscribers: aemerson, javed.absar, llvm-commits, tschuett
Differential Revision: https://reviews.llvm.org/D40361
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320973 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/AArch64/AArch64SVEInstrInfo.td | 6 | ||||
| -rw-r--r-- | lib/Target/AArch64/SVEInstrFormats.td | 62 |
2 files changed, 68 insertions, 0 deletions
diff --git a/lib/Target/AArch64/AArch64SVEInstrInfo.td b/lib/Target/AArch64/AArch64SVEInstrInfo.td index 7da0b28d22d..bcd7b60875a 100644 --- a/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -14,4 +14,10 @@ let Predicates = [HasSVE] in { defm ADD_ZZZ : sve_int_bin_cons_arit_0<0b000, "add">; defm SUB_ZZZ : sve_int_bin_cons_arit_0<0b001, "sub">; + + defm ZIP1_ZZZ : sve_int_perm_bin_perm_zz<0b000, "zip1">; + defm ZIP2_ZZZ : sve_int_perm_bin_perm_zz<0b001, "zip2">; + + defm ZIP1_PPP : sve_int_perm_bin_perm_pp<0b000, "zip1">; + defm ZIP2_PPP : sve_int_perm_bin_perm_pp<0b001, "zip2">; } diff --git a/lib/Target/AArch64/SVEInstrFormats.td b/lib/Target/AArch64/SVEInstrFormats.td index b4b46d731e3..15c1275f259 100644 --- a/lib/Target/AArch64/SVEInstrFormats.td +++ b/lib/Target/AArch64/SVEInstrFormats.td @@ -39,3 +39,65 @@ multiclass sve_int_bin_cons_arit_0<bits<3> opc, string asm> { def _S : sve_int_bin_cons_arit_0<0b10, opc, asm, ZPR32>; def _D : sve_int_bin_cons_arit_0<0b11, opc, asm, ZPR64>; } + +//===----------------------------------------------------------------------===// +// SVE Permute - In Lane Group +//===----------------------------------------------------------------------===// + +class sve_int_perm_bin_perm_zz<bits<3> opc, bits<2> sz8_64, string asm, + ZPRRegOp zprty> +: I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm), + asm, "\t$Zd, $Zn, $Zm", + "", + []>, Sched<[]> { + bits<5> Zd; + bits<5> Zm; + bits<5> Zn; + let Inst{31-24} = 0b00000101; + let Inst{23-22} = sz8_64; + let Inst{21} = 0b1; + let Inst{20-16} = Zm; + let Inst{15-13} = 0b011; + let Inst{12-10} = opc; + let Inst{9-5} = Zn; + let Inst{4-0} = Zd; +} + +multiclass sve_int_perm_bin_perm_zz<bits<3> opc, string asm> { + def _B : sve_int_perm_bin_perm_zz<opc, 0b00, asm, ZPR8>; + def _H : sve_int_perm_bin_perm_zz<opc, 0b01, asm, ZPR16>; + def _S : sve_int_perm_bin_perm_zz<opc, 0b10, asm, ZPR32>; + def _D : sve_int_perm_bin_perm_zz<opc, 0b11, asm, ZPR64>; +} + +//===----------------------------------------------------------------------===// +// SVE Permute - Predicates Group +//===----------------------------------------------------------------------===// + +class sve_int_perm_bin_perm_pp<bits<3> opc, bits<2> sz8_64, string asm, + PPRRegOp pprty> +: I<(outs pprty:$Pd), (ins pprty:$Pn, pprty:$Pm), + asm, "\t$Pd, $Pn, $Pm", + "", + []>, Sched<[]> { + bits<4> Pd; + bits<4> Pm; + bits<4> Pn; + let Inst{31-24} = 0b00000101; + let Inst{23-22} = sz8_64; + let Inst{21-20} = 0b10; + let Inst{19-16} = Pm; + let Inst{15-13} = 0b010; + let Inst{12-10} = opc; + let Inst{9} = 0b0; + let Inst{8-5} = Pn; + let Inst{4} = 0b0; + let Inst{3-0} = Pd; +} + +multiclass sve_int_perm_bin_perm_pp<bits<3> opc, string asm> { + def _B : sve_int_perm_bin_perm_pp<opc, 0b00, asm, PPR8>; + def _H : sve_int_perm_bin_perm_pp<opc, 0b01, asm, PPR16>; + def _S : sve_int_perm_bin_perm_pp<opc, 0b10, asm, PPR32>; + def _D : sve_int_perm_bin_perm_pp<opc, 0b11, asm, PPR64>; +}
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