diff options
author | Craig Topper <craig.topper@intel.com> | 2017-08-17 01:48:00 +0000 |
---|---|---|
committer | Craig Topper <craig.topper@intel.com> | 2017-08-17 01:48:00 +0000 |
commit | 4ddf75d9dc2a29b3ae4eb0e888e96b2a75874d7c (patch) | |
tree | 9b61ebab11a9a7a5c7f5dab6edf3d86b5e3e9bba /lib | |
parent | 85bef5a5c4c8a56a9b8ef9e815d88d03faee7876 (diff) |
[X86] Remove patterns for PALIGNR with non-vXi8 types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311058 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/Target/X86/X86InstrAVX512.td | 18 | ||||
-rw-r--r-- | lib/Target/X86/X86InstrFragmentsSIMD.td | 6 | ||||
-rw-r--r-- | lib/Target/X86/X86InstrSSE.td | 18 |
3 files changed, 5 insertions, 37 deletions
diff --git a/lib/Target/X86/X86InstrAVX512.td b/lib/Target/X86/X86InstrAVX512.td index 25a0baa2687..8e8461e0bda 100644 --- a/lib/Target/X86/X86InstrAVX512.td +++ b/lib/Target/X86/X86InstrAVX512.td @@ -9339,26 +9339,8 @@ defm VALIGND: avx512_valign<"valignd", avx512vl_i32_info>, defm VALIGNQ: avx512_valign<"valignq", avx512vl_i64_info>, EVEX_CD8<64, CD8VF>, VEX_W; -multiclass avx512_vpalignr_lowering<X86VectorVTInfo _ , list<Predicate> p>{ - let Predicates = p in - def NAME#_.VTName#rri: - Pat<(_.VT (X86PAlignr _.RC:$src1, _.RC:$src2, (i8 imm:$imm))), - (!cast<Instruction>(NAME#_.ZSuffix#rri) - _.RC:$src1, _.RC:$src2, imm:$imm)>; -} - -multiclass avx512_vpalignr_lowering_common<AVX512VLVectorVTInfo _>: - avx512_vpalignr_lowering<_.info512, [HasBWI]>, - avx512_vpalignr_lowering<_.info128, [HasBWI, HasVLX]>, - avx512_vpalignr_lowering<_.info256, [HasBWI, HasVLX]>; - defm VPALIGNR: avx512_common_3Op_rm_imm8<0x0F, X86PAlignr, "vpalignr" , avx512vl_i8_info, avx512vl_i8_info>, - avx512_vpalignr_lowering_common<avx512vl_i16_info>, - avx512_vpalignr_lowering_common<avx512vl_i32_info>, - avx512_vpalignr_lowering_common<avx512vl_f32_info>, - avx512_vpalignr_lowering_common<avx512vl_i64_info>, - avx512_vpalignr_lowering_common<avx512vl_f64_info>, EVEX_CD8<8, CD8VF>; defm VDBPSADBW: avx512_common_3Op_rm_imm8<0x42, X86dbpsadbw, "vdbpsadbw" , diff --git a/lib/Target/X86/X86InstrFragmentsSIMD.td b/lib/Target/X86/X86InstrFragmentsSIMD.td index 6b136de61d2..bca26f961f3 100644 --- a/lib/Target/X86/X86InstrFragmentsSIMD.td +++ b/lib/Target/X86/X86InstrFragmentsSIMD.td @@ -352,7 +352,11 @@ def SDTFmaRound : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>, SDTCisSameAs<1,2>, SDTCisSameAs<1,3>, SDTCisFP<0>, SDTCisVT<4, i32>]>; -def X86PAlignr : SDNode<"X86ISD::PALIGNR", SDTShuff3OpI>; +def X86PAlignr : SDNode<"X86ISD::PALIGNR", + SDTypeProfile<1, 3, [SDTCVecEltisVT<0, i8>, + SDTCisSameAs<0,1>, + SDTCisSameAs<0,2>, + SDTCisVT<3, i8>]>>; def X86VAlign : SDNode<"X86ISD::VALIGN", SDTShuff3OpI>; def X86Conflict : SDNode<"X86ISD::CONFLICT", SDTIntUnaryOp>; diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index d1115dbc918..387bb285299 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -5537,34 +5537,16 @@ let Constraints = "$src1 = $dst", Predicates = [UseSSSE3] in defm PALIGNR : ssse3_palignr<"palignr">; let Predicates = [HasAVX2, NoVLX_Or_NoBWI] in { -def : Pat<(v8i32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))), - (VPALIGNRYrri VR256:$src1, VR256:$src2, imm:$imm)>; -def : Pat<(v8f32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))), - (VPALIGNRYrri VR256:$src1, VR256:$src2, imm:$imm)>; -def : Pat<(v16i16 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))), - (VPALIGNRYrri VR256:$src1, VR256:$src2, imm:$imm)>; def : Pat<(v32i8 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))), (VPALIGNRYrri VR256:$src1, VR256:$src2, imm:$imm)>; } let Predicates = [HasAVX, NoVLX_Or_NoBWI] in { -def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))), - (VPALIGNRrri VR128:$src1, VR128:$src2, imm:$imm)>; -def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))), - (VPALIGNRrri VR128:$src1, VR128:$src2, imm:$imm)>; -def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))), - (VPALIGNRrri VR128:$src1, VR128:$src2, imm:$imm)>; def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))), (VPALIGNRrri VR128:$src1, VR128:$src2, imm:$imm)>; } let Predicates = [UseSSSE3] in { -def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))), - (PALIGNRrri VR128:$src1, VR128:$src2, imm:$imm)>; -def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))), - (PALIGNRrri VR128:$src1, VR128:$src2, imm:$imm)>; -def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))), - (PALIGNRrri VR128:$src1, VR128:$src2, imm:$imm)>; def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))), (PALIGNRrri VR128:$src1, VR128:$src2, imm:$imm)>; } |