[Hexagon] Generate HVX code for vector sign-, zero- and any-extends

Implement any-extend as zero-extend.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321004 91177308-0d34-0410-b5e6-96231b3b80d8

4 files changed, 38 insertions, 0 deletions

diff --git a/lib/Target/Hexagon/HexagonISelLowering.cpp b/lib/Target/Hexagon/HexagonISelLowering.cpp
index 6387ac2ef67..dc9eed51f45 100644
--- a/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -2013,6 +2013,11 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
       setOperationAction(ISD::ADD,     T, Legal);
       setOperationAction(ISD::SUB,     T, Legal);
       setOperationAction(ISD::VSELECT, T, Legal);
+      if (T != ByteV) {
+        setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG,  T, Legal);
+        setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, T, Legal);
+        setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, T, Legal);
+      }
 
       setOperationAction(ISD::MUL,                T, Custom);
       setOperationAction(ISD::SETCC,              T, Custom);
diff --git a/lib/Target/Hexagon/HexagonISelLowering.h b/lib/Target/Hexagon/HexagonISelLowering.h
index 2705fcbf8d6..0619e2e4e7f 100644
--- a/lib/Target/Hexagon/HexagonISelLowering.h
+++ b/lib/Target/Hexagon/HexagonISelLowering.h
@@ -351,6 +351,7 @@ namespace HexagonISD {
     SDValue LowerHvxInsertSubvector(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerHvxMul(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerHvxSetCC(SDValue Op, SelectionDAG &DAG) const;
+    SDValue LowerHvxExtend(SDValue Op, SelectionDAG &DAG) const;
 
     std::pair<const TargetRegisterClass*, uint8_t>
     findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT)
diff --git a/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp b/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
index 652dffce841..c1d44cb0e7d 100644
--- a/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
+++ b/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
@@ -454,3 +454,10 @@ HexagonTargetLowering::LowerHvxSetCC(SDValue Op, SelectionDAG &DAG) const {
   return Negate ? getNode(Hexagon::V6_pred_not, dl, ResTy, {CmpV}, DAG)
                 : CmpV;
 }
+
+SDValue
+HexagonTargetLowering::LowerHvxExtend(SDValue Op, SelectionDAG &DAG) const {
+  // Sign- and zero-extends are legal.
+  assert(Op.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG);
+  return DAG.getZeroExtendVectorInReg(Op.getOperand(0), SDLoc(Op), ty(Op));
+}
diff --git a/lib/Target/Hexagon/HexagonPatterns.td b/lib/Target/Hexagon/HexagonPatterns.td
index f8507036bbf..e2120d3de2e 100644
--- a/lib/Target/Hexagon/HexagonPatterns.td
+++ b/lib/Target/Hexagon/HexagonPatterns.td
@@ -2910,6 +2910,9 @@ def HexagonVINSERTW0 : SDNode<"HexagonISD::VINSERTW0", SDTHexagonVINSERTW0>;
 def Combinev: OutPatFrag<(ops node:$Rs, node:$Rt),
   (REG_SEQUENCE HvxWR, $Rs, vsub_hi, $Rt, vsub_lo)>;
 
+def LoVec: OutPatFrag<(ops node:$Vs), (EXTRACT_SUBREG $Vs, vsub_lo)>;
+def HiVec: OutPatFrag<(ops node:$Vs), (EXTRACT_SUBREG $Vs, vsub_hi)>;
+
 let Predicates = [UseHVX] in {
   def: OpR_RR_pat<V6_vpackeb,  pf2<HexagonVPACKE>,     VecI8,  HVI8>;
   def: OpR_RR_pat<V6_vpackob,  pf2<HexagonVPACKO>,     VecI8,  HVI8>;
@@ -2957,4 +2960,26 @@ let Predicates = [UseHVX] in {
            (V6_vmux HvxQR:$Qu, HvxVR:$Vs, HvxVR:$Vt)>;
   def: Pat<(vselect HQ32:$Qu, HVI32:$Vs, HVI32:$Vt),
            (V6_vmux HvxQR:$Qu, HvxVR:$Vs, HvxVR:$Vt)>;
+
+  def: Pat<(VecPI16 (sext HVI8:$Vs)),  (V6_vsb HvxVR:$Vs)>;
+  def: Pat<(VecPI32 (sext HVI16:$Vs)), (V6_vsh HvxVR:$Vs)>;
+  def: Pat<(VecPI16 (zext HVI8:$Vs)),  (V6_vzb HvxVR:$Vs)>;
+  def: Pat<(VecPI32 (zext HVI16:$Vs)), (V6_vzh HvxVR:$Vs)>;
+
+  def: Pat<(sext_inreg HVI32:$Vs, v16i16),
+           (V6_vpackeb (LoVec (V6_vsh HvxVR:$Vs)),
+                       (HiVec (V6_vsh HvxVR:$Vs)))>;
+  def: Pat<(sext_inreg HVI32:$Vs, v32i16),
+           (V6_vpackeb (LoVec (V6_vsh HvxVR:$Vs)),
+                       (HiVec (V6_vsh HvxVR:$Vs)))>;
+
+  def: Pat<(VecI16 (sext_invec HVI8:$Vs)),  (LoVec (V6_vsb HvxVR:$Vs))>;
+  def: Pat<(VecI32 (sext_invec HVI16:$Vs)), (LoVec (V6_vsh HvxVR:$Vs))>;
+  def: Pat<(VecI32 (sext_invec HVI8:$Vs)),
+           (LoVec (V6_vsh (LoVec (V6_vsb HvxVR:$Vs))))>;
+
+  def: Pat<(VecI16 (zext_invec HVI8:$Vs)),  (LoVec (V6_vzb HvxVR:$Vs))>;
+  def: Pat<(VecI32 (zext_invec HVI16:$Vs)), (LoVec (V6_vzh HvxVR:$Vs))>;
+  def: Pat<(VecI32 (zext_invec HVI8:$Vs)),
+           (LoVec (V6_vzh (LoVec (V6_vzb HvxVR:$Vs))))>;
 }