Merging r329761:

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r329761 | gberry | 2018-04-10 14:43:03 -0700 (Tue, 10 Apr 2018) | 13 lines

[AArch64][Falkor] Fix bug in Falkor HWPF collision avoidance pass.

Summary:
When inserting MOVs to avoid Falkor HWPF collisions, the non-base
register operand of load instructions (e.g. a register offset) was not
being considered live, so it could potentially have been used as a
scratch register, clobbering the actual offset value.

Reviewers: mcrosier

Subscribers: rengolin, javed.absar, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D45502
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@330209 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 18 insertions, 0 deletions

diff --git a/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp b/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp
index d1ddb2e3ef7..0d00dab598d 100644
--- a/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp
+++ b/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp
@@ -46,6 +46,7 @@
 #include "llvm/Pass.h"
 #include "llvm/Support/Casting.h"
 #include "llvm/Support/Debug.h"
+#include "llvm/Support/DebugCounter.h"
 #include "llvm/Support/raw_ostream.h"
 #include <cassert>
 #include <iterator>
@@ -60,6 +61,8 @@ STATISTIC(NumCollisionsAvoided,
           "Number of HW prefetch tag collisions avoided");
 STATISTIC(NumCollisionsNotAvoided,
           "Number of HW prefetch tag collisions not avoided due to lack of regsiters");
+DEBUG_COUNTER(FixCounter, "falkor-hwpf",
+              "Controls which tag collisions are avoided");
 
 namespace {
 
@@ -729,6 +732,21 @@ void FalkorHWPFFix::runOnLoop(MachineLoop &L, MachineFunction &Fn) {
       bool Fixed = false;
       DEBUG(dbgs() << "Attempting to fix tag collision: " << MI);
 
+      if (!DebugCounter::shouldExecute(FixCounter)) {
+        DEBUG(dbgs() << "Skipping fix due to debug counter:\n  " << MI);
+        continue;
+      }
+
+      // Add the non-base registers of MI as live so we don't use them as
+      // scratch registers.
+      for (unsigned OpI = 0, OpE = MI.getNumOperands(); OpI < OpE; ++OpI) {
+        if (OpI == static_cast<unsigned>(LdI.BaseRegIdx))
+          continue;
+        MachineOperand &MO = MI.getOperand(OpI);
+        if (MO.isReg() && MO.readsReg())
+          LR.addReg(MO.getReg());
+      }
+
       for (unsigned ScratchReg : AArch64::GPR64RegClass) {
         if (!LR.available(ScratchReg) || MRI.isReserved(ScratchReg))
           continue;