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authorJonas Paulsson <paulsson@linux.vnet.ibm.com>2018-04-12 08:06:04 +0000
committerJonas Paulsson <paulsson@linux.vnet.ibm.com>2018-04-12 08:06:04 +0000
commit19d0394c5ae46866452880e266510363aa917a17 (patch)
tree9f1f5739cb86d94b1056e66343b0320ee5849b75 /lib/Target/SystemZ
parent273601eded587f619453e854ae8e47f9fae1eea8 (diff)
[SystemZ] Remove FullInstRWOverlapCheck from SchedMachineModels.
This is NFC, even though it caught just a few cases of overlapping regular expressions. Review: Ulrich Weigand git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329886 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/SystemZ')
-rw-r--r--lib/Target/SystemZ/SystemZScheduleZ13.td8
-rw-r--r--lib/Target/SystemZ/SystemZScheduleZ14.td8
-rw-r--r--lib/Target/SystemZ/SystemZScheduleZ196.td6
-rw-r--r--lib/Target/SystemZ/SystemZScheduleZEC12.td6
4 files changed, 10 insertions, 18 deletions
diff --git a/lib/Target/SystemZ/SystemZScheduleZ13.td b/lib/Target/SystemZ/SystemZScheduleZ13.td
index ab835f634e6..efe8c939d6e 100644
--- a/lib/Target/SystemZ/SystemZScheduleZ13.td
+++ b/lib/Target/SystemZ/SystemZScheduleZ13.td
@@ -24,9 +24,6 @@ def Z13Model : SchedMachineModel {
// Extra cycles for a mispredicted branch.
let MispredictPenalty = 20;
-
- // FIXME: Remove when all errors have been fixed.
- let FullInstRWOverlapCheck = 0;
}
let SchedModel = Z13Model in {
@@ -596,7 +593,8 @@ def : InstRW<[LSU, LSU, Lat5, GroupAlone], (instregex "LPD(G)?$")>;
def : InstRW<[LSU, Lat30, GroupAlone], (instregex "TR$")>;
def : InstRW<[FXa, FXa, FXa, LSU, LSU, Lat30, GroupAlone], (instregex "TRT$")>;
def : InstRW<[FXa, LSU, Lat30], (instregex "TRTR$")>;
-def : InstRW<[FXa, Lat30], (instregex "TR(TR)?(T)?(E|EOpt)?$")>;
+def : InstRW<[FXa, Lat30], (instregex "TRE$")>;
+def : InstRW<[FXa, Lat30], (instregex "TRT(R)?E(Opt)?$")>;
def : InstRW<[LSU, Lat30], (instregex "TR(T|O)(T|O)(Opt)?$")>;
def : InstRW<[FXa, Lat30], (instregex "CU(12|14|21|24|41|42)(Opt)?$")>;
def : InstRW<[FXa, Lat30], (instregex "(CUUTF|CUTFU)(Opt)?$")>;
@@ -880,7 +878,7 @@ def : InstRW<[VecFPd, Lat30], (instregex "DI(E|D)BR$")>;
// Compare
def : InstRW<[VecXsPm, LSU, Lat8], (instregex "(K|C)(E|D)B$")>;
-def : InstRW<[VecXsPm, Lat4], (instregex "(K|C)(E|D)BR?$")>;
+def : InstRW<[VecXsPm, Lat4], (instregex "(K|C)(E|D)BR$")>;
def : InstRW<[VecDF, VecDF, Lat20, GroupAlone], (instregex "(K|C)XBR$")>;
// Test Data Class
diff --git a/lib/Target/SystemZ/SystemZScheduleZ14.td b/lib/Target/SystemZ/SystemZScheduleZ14.td
index e60e5583b50..4113e868cd0 100644
--- a/lib/Target/SystemZ/SystemZScheduleZ14.td
+++ b/lib/Target/SystemZ/SystemZScheduleZ14.td
@@ -24,9 +24,6 @@ def Z14Model : SchedMachineModel {
// Extra cycles for a mispredicted branch.
let MispredictPenalty = 20;
-
- // FIXME: Remove when all errors have been fixed.
- let FullInstRWOverlapCheck = 0;
}
let SchedModel = Z14Model in {
@@ -604,7 +601,8 @@ def : InstRW<[LSU, LSU, Lat5, GroupAlone], (instregex "LPD(G)?$")>;
def : InstRW<[LSU, Lat30, GroupAlone], (instregex "TR$")>;
def : InstRW<[FXa, FXa, FXa, LSU, LSU, Lat30, GroupAlone], (instregex "TRT$")>;
def : InstRW<[FXa, LSU, Lat30], (instregex "TRTR$")>;
-def : InstRW<[FXa, Lat30], (instregex "TR(TR)?(T)?(E|EOpt)?$")>;
+def : InstRW<[FXa, Lat30], (instregex "TRE$")>;
+def : InstRW<[FXa, Lat30], (instregex "TRT(R)?E(Opt)?$")>;
def : InstRW<[LSU, Lat30], (instregex "TR(T|O)(T|O)(Opt)?$")>;
def : InstRW<[FXa, Lat30], (instregex "CU(12|14|21|24|41|42)(Opt)?$")>;
def : InstRW<[FXa, Lat30], (instregex "(CUUTF|CUTFU)(Opt)?$")>;
@@ -897,7 +895,7 @@ def : InstRW<[VecFPd, Lat30], (instregex "DI(E|D)BR$")>;
// Compare
def : InstRW<[VecXsPm, LSU, Lat8], (instregex "(K|C)(E|D)B$")>;
-def : InstRW<[VecXsPm, Lat4], (instregex "(K|C)(E|D)BR?$")>;
+def : InstRW<[VecXsPm, Lat4], (instregex "(K|C)(E|D)BR$")>;
def : InstRW<[VecDF, VecDF, Lat20, GroupAlone], (instregex "(K|C)XBR$")>;
// Test Data Class
diff --git a/lib/Target/SystemZ/SystemZScheduleZ196.td b/lib/Target/SystemZ/SystemZScheduleZ196.td
index 43d18aa54a5..1eb24208a1c 100644
--- a/lib/Target/SystemZ/SystemZScheduleZ196.td
+++ b/lib/Target/SystemZ/SystemZScheduleZ196.td
@@ -24,9 +24,6 @@ def Z196Model : SchedMachineModel {
// Extra cycles for a mispredicted branch.
let MispredictPenalty = 16;
-
- // FIXME: Remove when all errors have been fixed.
- let FullInstRWOverlapCheck = 0;
}
let SchedModel = Z196Model in {
@@ -555,7 +552,8 @@ def : InstRW<[LSU, LSU, Lat5, GroupAlone], (instregex "LPD(G)?$")>;
def : InstRW<[LSU, Lat30, GroupAlone], (instregex "TR$")>;
def : InstRW<[LSU, Lat30, GroupAlone], (instregex "TRT$")>;
def : InstRW<[FXU, LSU, Lat30], (instregex "TRTR$")>;
-def : InstRW<[FXU, Lat30], (instregex "TR(TR)?(T)?(E|EOpt)?$")>;
+def : InstRW<[FXU, Lat30], (instregex "TRE$")>;
+def : InstRW<[FXU, Lat30], (instregex "TRT(R)?E(Opt)?$")>;
def : InstRW<[LSU, Lat30], (instregex "TR(T|O)(T|O)(Opt)?$")>;
def : InstRW<[FXU, Lat30], (instregex "CU(12|14|21|24|41|42)(Opt)?$")>;
def : InstRW<[FXU, Lat30], (instregex "(CUUTF|CUTFU)(Opt)?$")>;
diff --git a/lib/Target/SystemZ/SystemZScheduleZEC12.td b/lib/Target/SystemZ/SystemZScheduleZEC12.td
index c7f9a6e7cb6..d8047a72337 100644
--- a/lib/Target/SystemZ/SystemZScheduleZEC12.td
+++ b/lib/Target/SystemZ/SystemZScheduleZEC12.td
@@ -24,9 +24,6 @@ def ZEC12Model : SchedMachineModel {
// Extra cycles for a mispredicted branch.
let MispredictPenalty = 16;
-
- // FIXME: Remove when all errors have been fixed.
- let FullInstRWOverlapCheck = 0;
}
let SchedModel = ZEC12Model in {
@@ -567,7 +564,8 @@ def : InstRW<[LSU, LSU, Lat5, GroupAlone], (instregex "LPD(G)?$")>;
def : InstRW<[LSU, Lat30, GroupAlone], (instregex "TR$")>;
def : InstRW<[FXU, FXU, FXU, LSU, LSU, Lat30, GroupAlone], (instregex "TRT$")>;
def : InstRW<[FXU, LSU, Lat30], (instregex "TRTR$")>;
-def : InstRW<[FXU, Lat30], (instregex "TR(TR)?(T)?(E|EOpt)?$")>;
+def : InstRW<[FXU, Lat30], (instregex "TRE$")>;
+def : InstRW<[FXU, Lat30], (instregex "TRT(R)?E(Opt)?$")>;
def : InstRW<[LSU, Lat30], (instregex "TR(T|O)(T|O)(Opt)?$")>;
def : InstRW<[FXU, Lat30], (instregex "CU(12|14|21|24|41|42)(Opt)?$")>;
def : InstRW<[FXU, Lat30], (instregex "(CUUTF|CUTFU)(Opt)?$")>;