diff options
| author | Alex Bradbury <asb@lowrisc.org> | 2017-11-08 09:26:06 +0000 |
|---|---|---|
| committer | Alex Bradbury <asb@lowrisc.org> | 2017-11-08 09:26:06 +0000 |
| commit | 4d211caa3764ce1f205e8bc8cfa579735633fb59 (patch) | |
| tree | 3f01a9c7d412fc25bdc08470ec98e403201b80b2 /lib/Target/RISCV | |
| parent | 19b50e8dffa341a1790bcb72f8cbf095bea4ee9f (diff) | |
[NFCI] Ensure TargetOpcode::* are compatible with guessInstructionProperties=0
rL162640 introduced CodeGenTarget::guessInstructionProperties. If a target
sets guessInstructionProperties=0 in its FooInstrInfo, tablegen will error if
it has to guess properties from patterns. Unfortunately,
guessInstructionProperties=0 can't be used with current upstream LLVM as
instructions in the TargetOpcode namespace are always included and sometimes
have inferred properties for mayLoad, mayStore, and hasSideEffects. This patch
provides the simplest possible fix to this problem, setting default values for
these fields in the TargetOpcode scope. There is no intended functional
change, as the explicitly set properties should match what was previously
inferred. A number of the instructions had hasSideEffects=1 inferred
unintentionally. This patch makes it explicit, while future patches (such as
D37097) correct the property.
Differential Revision: https://reviews.llvm.org/D37065
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317674 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/RISCV')
| -rw-r--r-- | lib/Target/RISCV/RISCV.td | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/lib/Target/RISCV/RISCV.td b/lib/Target/RISCV/RISCV.td index 54aa570e13b..da919acad36 100644 --- a/lib/Target/RISCV/RISCV.td +++ b/lib/Target/RISCV/RISCV.td @@ -40,9 +40,7 @@ def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>; //===----------------------------------------------------------------------===// def RISCVInstrInfo : InstrInfo { - // TODO: disable guessInstructionProperties when - // https://reviews.llvm.org/D37065 lands. - let guessInstructionProperties = 1; + let guessInstructionProperties = 0; } def RISCVAsmParser : AsmParser { |