[RISCV] MC layer support for the standard RV32D instruction set extension

As the FPR32 and FPR64 registers have the same names, use 
validateTargetOperandClass in RISCVAsmParser to coerce a parsed FPR32 to an 
FPR64 when necessary. The rest of this patch is very similar to the RV32F 
patch.

Differential Revision: https://reviews.llvm.org/D39895


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320023 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 8 insertions, 0 deletions

diff --git a/lib/Target/RISCV/RISCV.td b/lib/Target/RISCV/RISCV.td
index 2a64ed5ace9..3ebf76b8e59 100644
--- a/lib/Target/RISCV/RISCV.td
+++ b/lib/Target/RISCV/RISCV.td
@@ -31,6 +31,13 @@ def FeatureStdExtF
 def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">,
                            AssemblerPredicate<"FeatureStdExtF">;
 
+def FeatureStdExtD
+    : SubtargetFeature<"d", "HasStdExtD", "true",
+                       "'D' (Double-Precision Floating-Point)",
+                       [FeatureStdExtF]>;
+def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">,
+                           AssemblerPredicate<"FeatureStdExtD">;
+
 def Feature64Bit
     : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">;
 
@@ -63,6 +70,7 @@ def RISCVInstrInfo : InstrInfo {
 
 def RISCVAsmParser : AsmParser {
   let ShouldEmitMatchRegisterAltName = 1;
+  let AllowDuplicateRegisterNames = 1;
 }
 
 def RISCV : Target {