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| author | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2017-12-15 14:17:45 +0000 |
|---|---|---|
| committer | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2017-12-15 14:17:45 +0000 |
| commit | e41a42810911a5f61245e659762eefa8442d31a6 (patch) | |
| tree | 9ee68dd1b877c7929962b4177eb382238ad3a863 /lib/Target/PowerPC/PPCInstrInfo.cpp | |
| parent | ccd83515f5632122bad16b45f965841e393b741a (diff) | |
Fix the second build bot break introduced by r320791.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320811 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCInstrInfo.cpp')
| -rw-r--r-- | lib/Target/PowerPC/PPCInstrInfo.cpp | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp index 879bb4c797e..031e6689f18 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -2286,6 +2286,13 @@ MachineInstr *PPCInstrInfo::getConstantDefMI(MachineInstr &MI, MachineBasicBlock::reverse_iterator E = MI.getParent()->rend(), It = MI; It++; unsigned Reg = MI.getOperand(i).getReg(); + // MachineInstr::readsRegister only returns true if the machine + // instruction reads the exact register or its super-register. It + // does not consider uses of sub-registers which seems like strange + // behaviour. Nonetheless, if we end up with a 64-bit register here, + // get the corresponding 32-bit register to check. + if (PPC::G8RCRegClass.contains(Reg)) + Reg = Reg - PPC::X0 + PPC::R0; // Is this register defined by a load-immediate in this block? for ( ; It != E; ++It) { |