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authorKrzysztof Parzyszek <kparzysz@codeaurora.org>2016-12-16 19:11:56 +0000
committerKrzysztof Parzyszek <kparzysz@codeaurora.org>2016-12-16 19:11:56 +0000
commit308c60d0cbdd653eec8139fb30c02def7bd223a8 (patch)
tree0b894099c872bee08b36aa83926aa262b2c138e0 /lib/Target/Hexagon/RDFGraph.cpp
parent83c848589954188246c59604106ccd8f691a1b2c (diff)
Implement LaneBitmask::any(), use it to replace !none(), NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@289974 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Hexagon/RDFGraph.cpp')
-rw-r--r--lib/Target/Hexagon/RDFGraph.cpp8
1 files changed, 4 insertions, 4 deletions
diff --git a/lib/Target/Hexagon/RDFGraph.cpp b/lib/Target/Hexagon/RDFGraph.cpp
index 04052b74a04..33c3f03790f 100644
--- a/lib/Target/Hexagon/RDFGraph.cpp
+++ b/lib/Target/Hexagon/RDFGraph.cpp
@@ -662,7 +662,7 @@ bool RegisterAggr::hasAliasOf(RegisterRef RR) const {
RegisterRef NR = normalize(RR);
auto F = Masks.find(NR.Reg);
if (F != Masks.end()) {
- if (!(F->second & NR.Mask).none())
+ if ((F->second & NR.Mask).any())
return true;
}
if (CheckUnits) {
@@ -1089,7 +1089,7 @@ RegisterRef DataFlowGraph::normalizeRef(RegisterRef RR) const {
RegisterRef DataFlowGraph::restrictRef(RegisterRef AR, RegisterRef BR) const {
if (AR.Reg == BR.Reg) {
LaneBitmask M = AR.Mask & BR.Mask;
- return !M.none() ? RegisterRef(AR.Reg, M) : RegisterRef();
+ return M.any() ? RegisterRef(AR.Reg, M) : RegisterRef();
}
#ifndef NDEBUG
RegisterRef NAR = normalizeRef(AR);
@@ -1221,7 +1221,7 @@ bool DataFlowGraph::alias(RegisterRef RA, RegisterRef RB) const {
// while the lane mask of r2 in d1 may be 0b0001.
LaneBitmask LA = PA.second & RA.Mask;
LaneBitmask LB = PB.second & RB.Mask;
- if (!LA.none() && !LB.none()) {
+ if (LA.any() && LB.any()) {
unsigned Root = *MCRegUnitRootIterator(PA.first, &TRI);
// If register units were guaranteed to only have 1 bit in any lane
// mask, the code below would not be necessary. This is because LA
@@ -1232,7 +1232,7 @@ bool DataFlowGraph::alias(RegisterRef RA, RegisterRef RB) const {
const TargetRegisterClass &RC = *TRI.getMinimalPhysRegClass(Root);
LaneBitmask MaskA = TRI.reverseComposeSubRegIndexLaneMask(SubA, LA);
LaneBitmask MaskB = TRI.reverseComposeSubRegIndexLaneMask(SubB, LB);
- if (!(MaskA & MaskB & RC.LaneMask).none())
+ if ((MaskA & MaskB & RC.LaneMask).any())
return true;
}