diff options
| author | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2018-06-19 17:26:20 +0000 |
|---|---|---|
| committer | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2018-06-19 17:26:20 +0000 |
| commit | 3e9f1c2ce41660bdc3917ca3271075709009a87b (patch) | |
| tree | cba53f9c2d48cf72316a57a28fb8b71534ba0cee /lib/Target/Hexagon/HexagonVLIWPacketizer.cpp | |
| parent | b07f54afdc8b1fb656efa91e2ba45d471dbca776 (diff) | |
[Hexagon] Enforce restrictions on packetizing cache instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335061 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Hexagon/HexagonVLIWPacketizer.cpp')
| -rw-r--r-- | lib/Target/Hexagon/HexagonVLIWPacketizer.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp index e44c7237a7e..ae974712e81 100644 --- a/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp +++ b/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp @@ -1115,6 +1115,10 @@ static bool cannotCoexistAsymm(const MachineInstr &MI, const MachineInstr &MJ, case Hexagon::S4_stored_locked: case Hexagon::L2_loadw_locked: case Hexagon::L4_loadd_locked: + case Hexagon::Y2_dccleana: + case Hexagon::Y2_dccleaninva: + case Hexagon::Y2_dcinva: + case Hexagon::Y2_dczeroa: case Hexagon::Y4_l2fetch: case Hexagon::Y5_l2fetch: { // These instructions can only be grouped with ALU32 or non-floating-point |