diff options
author | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2017-02-07 17:42:11 +0000 |
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committer | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2017-02-07 17:42:11 +0000 |
commit | ab8079ed2a42d286bc422328061a6ffc28115512 (patch) | |
tree | 42d53403cf9a555ae7a677cab84cd8b29d2b8328 /lib/Target/Hexagon/HexagonAsmPrinter.cpp | |
parent | 4e66158a93c7874911cedc2314c3fcd4811bf8ef (diff) |
[Hexagon] Remove encoding bits from mapped instructions
- Map A2_zxtb to A2_andir.
- Map PS_call_nr J2_call.
- Map A2_tfr[t|f][new] to A2_padd[t|f][new].
Patch by Colin LeMahieu.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294320 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Hexagon/HexagonAsmPrinter.cpp')
-rw-r--r-- | lib/Target/Hexagon/HexagonAsmPrinter.cpp | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/lib/Target/Hexagon/HexagonAsmPrinter.cpp b/lib/Target/Hexagon/HexagonAsmPrinter.cpp index 54db5ad4374..01ba1ccd37f 100644 --- a/lib/Target/Hexagon/HexagonAsmPrinter.cpp +++ b/lib/Target/Hexagon/HexagonAsmPrinter.cpp @@ -282,6 +282,36 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst, break; } + case Hexagon::A2_tfrf: { + Inst.setOpcode(Hexagon::A2_paddif); + Inst.addOperand(MCOperand::createExpr(MCConstantExpr::create(0, OutContext))); + break; + } + + case Hexagon::A2_tfrt: { + Inst.setOpcode(Hexagon::A2_paddit); + Inst.addOperand(MCOperand::createExpr(MCConstantExpr::create(0, OutContext))); + break; + } + + case Hexagon::A2_tfrfnew: { + Inst.setOpcode(Hexagon::A2_paddifnew); + Inst.addOperand(MCOperand::createExpr(MCConstantExpr::create(0, OutContext))); + break; + } + + case Hexagon::A2_tfrtnew: { + Inst.setOpcode(Hexagon::A2_padditnew); + Inst.addOperand(MCOperand::createExpr(MCConstantExpr::create(0, OutContext))); + break; + } + + case Hexagon::A2_zxtb: { + Inst.setOpcode(Hexagon::A2_andir); + Inst.addOperand(MCOperand::createExpr(MCConstantExpr::create(255, OutContext))); + break; + } + // "$dst = CONST64(#$src1)", case Hexagon::CONST64: if (!OutStreamer->hasRawTextSupport()) { @@ -376,6 +406,9 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst, Rs.setReg(getHexagonRegisterPair(Rs.getReg(), RI)); return; } + case Hexagon::PS_call_nr: + Inst.setOpcode(Hexagon::J2_call); + break; case Hexagon::S5_asrhub_rnd_sat_goodsyntax: { MCOperand &MO = MappedInst.getOperand(2); int64_t Imm; |