diff options
author | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2016-11-09 16:19:08 +0000 |
---|---|---|
committer | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2016-11-09 16:19:08 +0000 |
commit | 5d84a0761edf17e5fde97f200e525e066be54b78 (patch) | |
tree | a7cba0172a33e529248dbaa5219a236953624ec1 /lib/Target/Hexagon/HexagonAsmPrinter.cpp | |
parent | 0f8962800129ad12f03f681b1a4205488680b0f7 (diff) |
[Hexagon] Separate Hexagon subreg indices for different register classes
For pairs of 32-bit registers: isub_lo, isub_hi.
For pairs of vector registers: vsub_lo, vsub_hi.
Add generic subreg indices: ps_sub_lo, ps_sub_hi, and a function
HexagonRegisterInfo::getHexagonSubRegIndex(RegClass, GenericSubreg)
that returns the appropriate subreg index for RegClass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286377 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Hexagon/HexagonAsmPrinter.cpp')
-rw-r--r-- | lib/Target/Hexagon/HexagonAsmPrinter.cpp | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/lib/Target/Hexagon/HexagonAsmPrinter.cpp b/lib/Target/Hexagon/HexagonAsmPrinter.cpp index 7219977eebe..54db5ad4374 100644 --- a/lib/Target/Hexagon/HexagonAsmPrinter.cpp +++ b/lib/Target/Hexagon/HexagonAsmPrinter.cpp @@ -152,8 +152,8 @@ bool HexagonAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, // This should be an assert in the frontend. if (Hexagon::DoubleRegsRegClass.contains(RegNumber)) RegNumber = TRI->getSubReg(RegNumber, ExtraCode[0] == 'L' ? - Hexagon::subreg_loreg : - Hexagon::subreg_hireg); + Hexagon::isub_lo : + Hexagon::isub_hi); OS << HexagonInstPrinter::getRegisterName(RegNumber); return false; } @@ -414,8 +414,8 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst, TmpInst.setOpcode(Hexagon::A2_combinew); TmpInst.addOperand(MappedInst.getOperand(0)); MCOperand &MO1 = MappedInst.getOperand(1); - unsigned High = RI->getSubReg(MO1.getReg(), Hexagon::subreg_hireg); - unsigned Low = RI->getSubReg(MO1.getReg(), Hexagon::subreg_loreg); + unsigned High = RI->getSubReg(MO1.getReg(), Hexagon::isub_hi); + unsigned Low = RI->getSubReg(MO1.getReg(), Hexagon::isub_lo); // Add a new operand for the second register in the pair. TmpInst.addOperand(MCOperand::createReg(High)); TmpInst.addOperand(MCOperand::createReg(Low)); @@ -487,8 +487,8 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst, // Translate a "$Rdd = $Rss" to "$Rdd = combine($Rs, $Rt)" case Hexagon::A2_tfrp: { MCOperand &MO = MappedInst.getOperand(1); - unsigned High = RI->getSubReg(MO.getReg(), Hexagon::subreg_hireg); - unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::subreg_loreg); + unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi); + unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo); MO.setReg(High); // Add a new operand for the second register in the pair. MappedInst.addOperand(MCOperand::createReg(Low)); @@ -499,8 +499,8 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst, case Hexagon::A2_tfrpt: case Hexagon::A2_tfrpf: { MCOperand &MO = MappedInst.getOperand(2); - unsigned High = RI->getSubReg(MO.getReg(), Hexagon::subreg_hireg); - unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::subreg_loreg); + unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi); + unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo); MO.setReg(High); // Add a new operand for the second register in the pair. MappedInst.addOperand(MCOperand::createReg(Low)); @@ -512,8 +512,8 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst, case Hexagon::A2_tfrptnew: case Hexagon::A2_tfrpfnew: { MCOperand &MO = MappedInst.getOperand(2); - unsigned High = RI->getSubReg(MO.getReg(), Hexagon::subreg_hireg); - unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::subreg_loreg); + unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi); + unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo); MO.setReg(High); // Add a new operand for the second register in the pair. MappedInst.addOperand(MCOperand::createReg(Low)); |