[Hexagon] Enabling ASM parsing on Hexagon backend and adding instruction parsing tests. General updating of the code emission.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252443 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 9 insertions, 0 deletions

diff --git a/lib/Target/Hexagon/Hexagon.td b/lib/Target/Hexagon/Hexagon.td
index c0631c4bbbd..ff70fb27b27 100644
--- a/lib/Target/Hexagon/Hexagon.td
+++ b/lib/Target/Hexagon/Hexagon.td
@@ -30,6 +30,9 @@ def ArchV60: SubtargetFeature<"v60", "HexagonArchVersion", "V60", "Hexagon V60">
 // Hexagon ISA Extensions
 def ExtensionHVX: SubtargetFeature<"hvx", "UseHVXOps",
                                    "true", "Hexagon HVX instructions">;
+def ExtensionHVXDbl: SubtargetFeature<"hvxDbl", "UseHVXDblOps",
+                                   "true", "Hexagon HVX Double instructions">;
+
 //===----------------------------------------------------------------------===//
 // Hexagon Instruction Predicate Definitions.
 //===----------------------------------------------------------------------===//
@@ -212,7 +215,13 @@ def : Proc<"hexagonv5",  HexagonModelV4,
 // Declare the target which we are implementing
 //===----------------------------------------------------------------------===//
 
+def HexagonAsmParserVariant : AsmParserVariant {
+  int Variant = 0;
+  string TokenizingCharacters = "#()=:.<>!+*";
+}
+
 def Hexagon : Target {
   // Pull in Instruction Info:
   let InstructionSet = HexagonInstrInfo;
+  let AssemblyParserVariants = [HexagonAsmParserVariant];
 }