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| author | Jia Liu <proljc@gmail.com> | 2012-02-18 12:03:15 +0000 |
|---|---|---|
| committer | Jia Liu <proljc@gmail.com> | 2012-02-18 12:03:15 +0000 |
| commit | 31d157ae1ac2cd9c787dc3c1d28e64c682803844 (patch) | |
| tree | f26bc6f243960a904162b8ef10f0687800a41191 /lib/Target/Hexagon/Hexagon.td | |
| parent | 107506f814f42af4a905156e7ce5dd9a2ca6c0c7 (diff) | |
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Hexagon/Hexagon.td')
| -rw-r--r-- | lib/Target/Hexagon/Hexagon.td | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/lib/Target/Hexagon/Hexagon.td b/lib/Target/Hexagon/Hexagon.td index 72939e6f1f7..ab5093dbfcf 100644 --- a/lib/Target/Hexagon/Hexagon.td +++ b/lib/Target/Hexagon/Hexagon.td @@ -1,4 +1,4 @@ -//===- Hexagon.td - Describe the Hexagon Target Machine ---------*- C++ -*-===// +//===-- Hexagon.td - Describe the Hexagon Target Machine --*- tablegen -*--===// // // The LLVM Compiler Infrastructure // @@ -7,6 +7,7 @@ // //===----------------------------------------------------------------------===// // +// This is the top level entry point for the Hexagon target. // //===----------------------------------------------------------------------===// @@ -18,8 +19,7 @@ include "llvm/Target/Target.td" //===----------------------------------------------------------------------===// // Hexagon Subtarget features. -// - +//===----------------------------------------------------------------------===// // Hexagon Archtectures def ArchV2 : SubtargetFeature<"v2", "HexagonArchVersion", "V2", |