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| author | Tom Stellard <tstellar@redhat.com> | 2018-04-09 16:38:02 +0000 |
|---|---|---|
| committer | Tom Stellard <tstellar@redhat.com> | 2018-04-09 16:38:02 +0000 |
| commit | a7769cbdb107428ce7bab197ec65aa96aa127020 (patch) | |
| tree | 5604fb7a323d848c2918c7288e211a9d71bf1741 /lib/Target/ARM/ARMBaseInstrInfo.cpp | |
| parent | aa0c91ae818e0b9e7981a42236dededc85997568 (diff) | |
Merging r326535:
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r326535 | jvesely | 2018-03-01 18:50:22 -0800 (Thu, 01 Mar 2018) | 6 lines
AMDGPU/GCN: Promote i16 ctpop
i16 capable ASICs do not support i16 operands for this instruction.
Add tablegen pattern to merge chained i16 additions.
Differential Revision: https://reviews.llvm.org/D43985
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@329589 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMBaseInstrInfo.cpp')
0 files changed, 0 insertions, 0 deletions