diff options
author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-12-29 17:18:18 +0000 |
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committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-12-29 17:18:18 +0000 |
commit | 8923569a3dd7d4f5a8bbc2b77a028f560024a000 (patch) | |
tree | ff4d912f73e91fe8c776a0b8f725bfc178f76084 /lib/Target/AMDGPU | |
parent | a6448ac97c5b18f940055501152a06fdfd875997 (diff) |
AMDGPU: Remove mayLoad/hasSideEffects from MIMG stores
Atomics still have hasSideEffects set on them because
of the mess that is the memory properties.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321556 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/AMDGPU')
-rw-r--r-- | lib/Target/AMDGPU/MIMGInstructions.td | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/lib/Target/AMDGPU/MIMGInstructions.td b/lib/Target/AMDGPU/MIMGInstructions.td index 30a2df51038..651265fc54d 100644 --- a/lib/Target/AMDGPU/MIMGInstructions.td +++ b/lib/Target/AMDGPU/MIMGInstructions.td @@ -71,9 +71,9 @@ class MIMG_Store_Helper <bits<7> op, string asm, r128:$r128, tfe:$tfe, lwe:$lwe, da:$da), asm#" $vdata, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da", dns>, MIMGe<op> { let ssamp = 0; - let mayLoad = 1; // TableGen requires this for matching with the intrinsics + let mayLoad = 0; let mayStore = 1; - let hasSideEffects = 1; + let hasSideEffects = 0; let hasPostISelHook = 0; let DisableWQM = 1; } @@ -103,10 +103,10 @@ class MIMG_Atomic_Helper <string asm, RegisterClass data_rc, (ins data_rc:$vdata, addr_rc:$vaddr, SReg_256:$srsrc, dmask:$dmask, unorm:$unorm, GLC:$glc, slc:$slc, r128:$r128, tfe:$tfe, lwe:$lwe, da:$da), - asm#" $vdst, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da" - > { + asm#" $vdst, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da"> { + let mayLoad = 1; let mayStore = 1; - let hasSideEffects = 1; + let hasSideEffects = 1; // FIXME: Remove this let hasPostISelHook = 0; let DisableWQM = 1; let Constraints = "$vdst = $vdata"; |