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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-11-30 22:51:26 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-11-30 22:51:26 +0000 |
| commit | 421983a9de53bfbfe1e9fc528cf2e96ea41f2463 (patch) | |
| tree | 80ed2d8787f37181a77abe4bd7abc00cda5d8bf4 /lib/Target/AMDGPU/SIISelLowering.cpp | |
| parent | a4d647d52ac02d958258c90398d12e6252f37147 (diff) | |
AMDGPU: Use gfx9 carry-less add/sub instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319491 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/AMDGPU/SIISelLowering.cpp')
| -rw-r--r-- | lib/Target/AMDGPU/SIISelLowering.cpp | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/lib/Target/AMDGPU/SIISelLowering.cpp b/lib/Target/AMDGPU/SIISelLowering.cpp index dd8756bfd11..bab7739511f 100644 --- a/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/lib/Target/AMDGPU/SIISelLowering.cpp @@ -226,6 +226,14 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM, setOperationAction(ISD::ADDCARRY, MVT::i32, Legal); setOperationAction(ISD::SUBCARRY, MVT::i32, Legal); +#if 0 + setOperationAction(ISD::ADDCARRY, MVT::i64, Legal); + setOperationAction(ISD::SUBCARRY, MVT::i64, Legal); +#endif + + //setOperationAction(ISD::ADDC, MVT::i64, Expand); + //setOperationAction(ISD::SUBC, MVT::i64, Expand); + // We only support LOAD/STORE and vector manipulation ops for vectors // with > 4 elements. for (MVT VT : {MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32, |