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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-06-02 18:02:42 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-06-02 18:02:42 +0000 |
| commit | 7796b916f8b36d078b5fc25f3af5571556e5811f (patch) | |
| tree | 1a554006c5c1f384cf0ff5d9bbf56b74f91f96b9 /lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | |
| parent | 8147ef137251fae557bbc40b21fe3468d2a9078b (diff) | |
AMDGPU: Register AMDGPUAlwaysInline
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304574 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/AMDGPU/AMDGPUTargetMachine.cpp')
| -rw-r--r-- | lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index 67c9a1987d3..404598ff473 100644 --- a/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -139,6 +139,7 @@ extern "C" void LLVMInitializeAMDGPUTarget() { initializeSIShrinkInstructionsPass(*PR); initializeSIFixControlFlowLiveIntervalsPass(*PR); initializeSILoadStoreOptimizerPass(*PR); + initializeAMDGPUAlwaysInlinePass(*PR); initializeAMDGPUAnnotateKernelFeaturesPass(*PR); initializeAMDGPUAnnotateUniformValuesPass(*PR); initializeAMDGPULowerIntrinsicsPass(*PR); |