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authorFrancis Visoiu Mistrih <francisvm@yahoo.com>2017-12-15 16:33:45 +0000
committerFrancis Visoiu Mistrih <francisvm@yahoo.com>2017-12-15 16:33:45 +0000
commit38e881da88fa50d763b25b2fa32c0ce808b15acf (patch)
tree715f99064ac12c2cc5e5bcba5e7c9aa3e2932e40 /lib/Target/AArch64
parentbab7762fc59cd5a1171897fdf2524dc1dcf5841c (diff)
[CodeGen] Print stack object references as %(fixed-)stack.0 in both MIR and debug output
Work towards the unification of MIR and debug output by printing `%stack.0` instead of `<fi#0>`, and `%fixed-stack.0` instead of `<fi#-4>` (supposing there are 4 fixed stack objects). Only debug syntax is affected. Differential Revision: https://reviews.llvm.org/D41027 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320827 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/AArch64')
-rw-r--r--lib/Target/AArch64/AArch64InstrInfo.cpp6
1 files changed, 3 insertions, 3 deletions
diff --git a/lib/Target/AArch64/AArch64InstrInfo.cpp b/lib/Target/AArch64/AArch64InstrInfo.cpp
index 9e12b1a0e70..74aee126d45 100644
--- a/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -2835,7 +2835,7 @@ MachineInstr *AArch64InstrInfo::foldMemoryOperandImpl(
// In this case we can still safely fold away the COPY and generate the
// following spill code:
//
- // STRXui %xzr, <fi#0>
+ // STRXui %xzr, %stack.0
//
// This also eliminates spilled cross register class COPYs (e.g. between x and
// d regs) of the same size. For example:
@@ -2891,7 +2891,7 @@ MachineInstr *AArch64InstrInfo::foldMemoryOperandImpl(
// where the physical register source can be widened and stored to the full
// virtual reg destination stack slot, in this case producing:
//
- // STRXui %xzr, <fi#0>
+ // STRXui %xzr, %stack.0
//
if (IsSpill && DstMO.isUndef() &&
TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
@@ -2939,7 +2939,7 @@ MachineInstr *AArch64InstrInfo::foldMemoryOperandImpl(
// where we can load the full virtual reg source stack slot, into the subreg
// destination, in this case producing:
//
- // LDRWui %0:sub_32<def,read-undef>, <fi#0>
+ // LDRWui %0:sub_32<def,read-undef>, %stack.0
//
if (IsFill && SrcMO.getSubReg() == 0 && DstMO.isUndef()) {
const TargetRegisterClass *FillRC;