diff options
author | Tim Northover <tnorthover@apple.com> | 2016-10-14 22:18:18 +0000 |
---|---|---|
committer | Tim Northover <tnorthover@apple.com> | 2016-10-14 22:18:18 +0000 |
commit | ee325b9e96fe1cbcc66ba62fdf65ac502577a23f (patch) | |
tree | 5efa678dee549f10d8781beb123843f72d7064a5 /lib/Target/AArch64 | |
parent | 6a2dc096c949c900fa0a35c9bed939b21cb3f6bc (diff) |
GlobalISel: rename legalizer components to match others.
The previous names were both misleading (the MachineLegalizer actually
contained the info tables) and inconsistent with the selector & translator (in
having a "Machine") prefix. This should make everything sensible again.
The only functional change is the name of a couple of command-line options.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284287 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/AArch64')
-rw-r--r-- | lib/Target/AArch64/AArch64LegalizerInfo.cpp (renamed from lib/Target/AArch64/AArch64MachineLegalizer.cpp) | 6 | ||||
-rw-r--r-- | lib/Target/AArch64/AArch64LegalizerInfo.h (renamed from lib/Target/AArch64/AArch64MachineLegalizer.h) | 8 | ||||
-rw-r--r-- | lib/Target/AArch64/AArch64Subtarget.cpp | 4 | ||||
-rw-r--r-- | lib/Target/AArch64/AArch64Subtarget.h | 2 | ||||
-rw-r--r-- | lib/Target/AArch64/AArch64TargetMachine.cpp | 12 | ||||
-rw-r--r-- | lib/Target/AArch64/CMakeLists.txt | 2 |
6 files changed, 17 insertions, 17 deletions
diff --git a/lib/Target/AArch64/AArch64MachineLegalizer.cpp b/lib/Target/AArch64/AArch64LegalizerInfo.cpp index 46261bca67c..b8f1136b23b 100644 --- a/lib/Target/AArch64/AArch64MachineLegalizer.cpp +++ b/lib/Target/AArch64/AArch64LegalizerInfo.cpp @@ -1,4 +1,4 @@ -//===- AArch64MachineLegalizer.cpp -------------------------------*- C++ -*-==// +//===- AArch64LegalizerInfo.cpp ----------------------------------*- C++ -*-==// // // The LLVM Compiler Infrastructure // @@ -12,7 +12,7 @@ /// \todo This should be generated by TableGen. //===----------------------------------------------------------------------===// -#include "AArch64MachineLegalizer.h" +#include "AArch64LegalizerInfo.h" #include "llvm/CodeGen/ValueTypes.h" #include "llvm/IR/Type.h" #include "llvm/IR/DerivedTypes.h" @@ -24,7 +24,7 @@ using namespace llvm; #error "You shouldn't build this" #endif -AArch64MachineLegalizer::AArch64MachineLegalizer() { +AArch64LegalizerInfo::AArch64LegalizerInfo() { using namespace TargetOpcode; const LLT p0 = LLT::pointer(0, 64); const LLT s1 = LLT::scalar(1); diff --git a/lib/Target/AArch64/AArch64MachineLegalizer.h b/lib/Target/AArch64/AArch64LegalizerInfo.h index 4e8d1f2ccb7..feacbef9f14 100644 --- a/lib/Target/AArch64/AArch64MachineLegalizer.h +++ b/lib/Target/AArch64/AArch64LegalizerInfo.h @@ -1,4 +1,4 @@ -//===- AArch64Machinelegalizer --------------------------------*- C++ -*-==// +//===- AArch64LegalizerInfo --------------------------------------*- C++ -*-==// // // The LLVM Compiler Infrastructure // @@ -15,16 +15,16 @@ #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64MACHINELEGALIZER_H #define LLVM_LIB_TARGET_AARCH64_AARCH64MACHINELEGALIZER_H -#include "llvm/CodeGen/GlobalISel/MachineLegalizer.h" +#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h" namespace llvm { class LLVMContext; /// This class provides the information for the target register banks. -class AArch64MachineLegalizer : public MachineLegalizer { +class AArch64LegalizerInfo : public LegalizerInfo { public: - AArch64MachineLegalizer(); + AArch64LegalizerInfo(); }; } // End llvm namespace. #endif diff --git a/lib/Target/AArch64/AArch64Subtarget.cpp b/lib/Target/AArch64/AArch64Subtarget.cpp index 61bfd7a0811..78a2631614e 100644 --- a/lib/Target/AArch64/AArch64Subtarget.cpp +++ b/lib/Target/AArch64/AArch64Subtarget.cpp @@ -105,9 +105,9 @@ const InstructionSelector *AArch64Subtarget::getInstructionSelector() const { return GISel->getInstructionSelector(); } -const MachineLegalizer *AArch64Subtarget::getMachineLegalizer() const { +const LegalizerInfo *AArch64Subtarget::getLegalizerInfo() const { assert(GISel && "Access to GlobalISel APIs not set"); - return GISel->getMachineLegalizer(); + return GISel->getLegalizerInfo(); } const RegisterBankInfo *AArch64Subtarget::getRegBankInfo() const { diff --git a/lib/Target/AArch64/AArch64Subtarget.h b/lib/Target/AArch64/AArch64Subtarget.h index a21dbd8322f..cdc5d741ae3 100644 --- a/lib/Target/AArch64/AArch64Subtarget.h +++ b/lib/Target/AArch64/AArch64Subtarget.h @@ -147,7 +147,7 @@ public: } const CallLowering *getCallLowering() const override; const InstructionSelector *getInstructionSelector() const override; - const MachineLegalizer *getMachineLegalizer() const override; + const LegalizerInfo *getLegalizerInfo() const override; const RegisterBankInfo *getRegBankInfo() const override; const Triple &getTargetTriple() const { return TargetTriple; } bool enableMachineScheduler() const override { return true; } diff --git a/lib/Target/AArch64/AArch64TargetMachine.cpp b/lib/Target/AArch64/AArch64TargetMachine.cpp index f0fd0543351..940c2397f16 100644 --- a/lib/Target/AArch64/AArch64TargetMachine.cpp +++ b/lib/Target/AArch64/AArch64TargetMachine.cpp @@ -13,14 +13,14 @@ #include "AArch64.h" #include "AArch64CallLowering.h" #include "AArch64InstructionSelector.h" -#include "AArch64MachineLegalizer.h" +#include "AArch64LegalizerInfo.h" #include "AArch64RegisterBankInfo.h" #include "AArch64TargetMachine.h" #include "AArch64TargetObjectFile.h" #include "AArch64TargetTransformInfo.h" #include "llvm/CodeGen/GlobalISel/IRTranslator.h" #include "llvm/CodeGen/GlobalISel/InstructionSelect.h" -#include "llvm/CodeGen/GlobalISel/MachineLegalizePass.h" +#include "llvm/CodeGen/GlobalISel/Legalizer.h" #include "llvm/CodeGen/GlobalISel/RegBankSelect.h" #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/RegAllocRegistry.h" @@ -202,7 +202,7 @@ namespace { struct AArch64GISelActualAccessor : public GISelAccessor { std::unique_ptr<CallLowering> CallLoweringInfo; std::unique_ptr<InstructionSelector> InstSelector; - std::unique_ptr<MachineLegalizer> Legalizer; + std::unique_ptr<LegalizerInfo> Legalizer; std::unique_ptr<RegisterBankInfo> RegBankInfo; const CallLowering *getCallLowering() const override { return CallLoweringInfo.get(); @@ -210,7 +210,7 @@ struct AArch64GISelActualAccessor : public GISelAccessor { const InstructionSelector *getInstructionSelector() const override { return InstSelector.get(); } - const class MachineLegalizer *getMachineLegalizer() const override { + const class LegalizerInfo *getLegalizerInfo() const override { return Legalizer.get(); } const RegisterBankInfo *getRegBankInfo() const override { @@ -247,7 +247,7 @@ AArch64TargetMachine::getSubtargetImpl(const Function &F) const { new AArch64GISelActualAccessor(); GISel->CallLoweringInfo.reset( new AArch64CallLowering(*I->getTargetLowering())); - GISel->Legalizer.reset(new AArch64MachineLegalizer()); + GISel->Legalizer.reset(new AArch64LegalizerInfo()); auto *RBI = new AArch64RegisterBankInfo(*I->getRegisterInfo()); @@ -399,7 +399,7 @@ bool AArch64PassConfig::addIRTranslator() { return false; } bool AArch64PassConfig::addLegalizeMachineIR() { - addPass(new MachineLegalizePass()); + addPass(new Legalizer()); return false; } bool AArch64PassConfig::addRegBankSelect() { diff --git a/lib/Target/AArch64/CMakeLists.txt b/lib/Target/AArch64/CMakeLists.txt index 9af0ed66840..300a6ea947e 100644 --- a/lib/Target/AArch64/CMakeLists.txt +++ b/lib/Target/AArch64/CMakeLists.txt @@ -20,7 +20,7 @@ add_public_tablegen_target(AArch64CommonTableGen) set(GLOBAL_ISEL_FILES AArch64CallLowering.cpp AArch64InstructionSelector.cpp - AArch64MachineLegalizer.cpp + AArch64LegalizerInfo.cpp AArch64RegisterBankInfo.cpp ) |