diff options
| author | Sander de Smalen <sander.desmalen@arm.com> | 2018-02-06 13:13:21 +0000 |
|---|---|---|
| committer | Sander de Smalen <sander.desmalen@arm.com> | 2018-02-06 13:13:21 +0000 |
| commit | e2da79543b4fa0aaeb885410d1a328468fe5b138 (patch) | |
| tree | 658a5817b695f5cf0933b8a8542575c2875713e6 /lib/Target/AArch64/Disassembler | |
| parent | bed04b64f4ab96f7ae2a59416c40d4abb18457f9 (diff) | |
[AArch64][SVE] Asm: Add AND_ZI instructions and aliases
Summary: Adds support for the SVE AND instruction with vector and logical-immediate operands, and their corresponding aliases.
Reviewers: fhahn, rengolin, samparker, echristo, aadg, kristof.beyls
Reviewed By: fhahn
Subscribers: aemerson, javed.absar, tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D42295
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@324343 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/AArch64/Disassembler')
| -rw-r--r-- | lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp b/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp index 583a07f6a7b..b4a554e0658 100644 --- a/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp +++ b/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp @@ -188,6 +188,10 @@ static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder); +static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst, + uint32_t insn, + uint64_t Address, + const void *Decoder); template<int Bits> static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder); @@ -1649,6 +1653,22 @@ static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, RegNo, Addr, Decoder); } +static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst, + uint32_t insn, + uint64_t Addr, + const void *Decoder) { + unsigned Zdn = fieldFromInstruction(insn, 0, 5); + unsigned imm = fieldFromInstruction(insn, 5, 13); + if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) + return Fail; + + // The same (tied) operand is added twice to the instruction. + DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); + DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); + Inst.addOperand(MCOperand::createImm(imm)); + return Success; +} + template<int Bits> static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder) { |