diff options
author | Daniel Sanders <daniel_l_sanders@apple.com> | 2017-01-13 10:53:57 +0000 |
---|---|---|
committer | Daniel Sanders <daniel_l_sanders@apple.com> | 2017-01-13 10:53:57 +0000 |
commit | e2892e1556057a158f8f4e2b29ad772ae818dfc5 (patch) | |
tree | c5abe384bcd06ecfb3b472f2a7c4ee95b08a7d8c /lib/Target/AArch64/AArch64RegisterBankInfo.h | |
parent | 93a4a6e6812526a2d922eb1fb12ecaea2b5ac188 (diff) |
[aarch64][globalisel] Move data into <Target>GenRegisterBankInfo. NFC.
Summary: Depends on D27809
Reviewers: t.p.northover, rovka, qcolombet, ab
Subscribers: aditya_nandakumar, aemerson, rengolin, vkalintiris, dberris, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D27976
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291897 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/AArch64/AArch64RegisterBankInfo.h')
-rw-r--r-- | lib/Target/AArch64/AArch64RegisterBankInfo.h | 71 |
1 files changed, 66 insertions, 5 deletions
diff --git a/lib/Target/AArch64/AArch64RegisterBankInfo.h b/lib/Target/AArch64/AArch64RegisterBankInfo.h index f763235049d..27358327b4f 100644 --- a/lib/Target/AArch64/AArch64RegisterBankInfo.h +++ b/lib/Target/AArch64/AArch64RegisterBankInfo.h @@ -27,14 +27,75 @@ enum { CCRRegBankID = 2, /// Conditional register: NZCV. NumRegisterBanks }; - -extern RegisterBank GPRRegBank; -extern RegisterBank FPRRegBank; -extern RegisterBank CCRRegBank; } // End AArch64 namespace. +class AArch64GenRegisterBankInfo : public RegisterBankInfo { +private: + static RegisterBank *RegBanks[]; + +protected: + AArch64GenRegisterBankInfo(); + +public: + static RegisterBankInfo::PartialMapping PartMappings[]; + static RegisterBankInfo::ValueMapping ValMappings[]; + static bool checkPartialMap(unsigned Idx, unsigned ValStartIdx, + unsigned ValLength, const RegisterBank &RB); + static bool checkValueMapImpl(unsigned Idx, unsigned FirstInBank, + unsigned Size, unsigned Offset); + enum PartialMappingIdx { + PMI_None = -1, + PMI_GPR32 = 1, + PMI_GPR64, + PMI_FPR32, + PMI_FPR64, + PMI_FPR128, + PMI_FPR256, + PMI_FPR512, + PMI_FirstGPR = PMI_GPR32, + PMI_LastGPR = PMI_GPR64, + PMI_FirstFPR = PMI_FPR32, + PMI_LastFPR = PMI_FPR512, + PMI_Min = PMI_FirstGPR, + }; + + enum ValueMappingIdx { + First3OpsIdx = 0, + Last3OpsIdx = 18, + DistanceBetweenRegBanks = 3, + FirstCrossRegCpyIdx = 21, + LastCrossRegCpyIdx = 27, + DistanceBetweenCrossRegCpy = 2 + }; + + static bool checkPartialMappingIdx(PartialMappingIdx FirstAlias, + PartialMappingIdx LastAlias, + ArrayRef<PartialMappingIdx> Order) { + if (Order.front() != FirstAlias) + return false; + if (Order.back() != LastAlias) + return false; + if (Order.front() > Order.back()) + return false; + + PartialMappingIdx Previous = Order.front(); + bool First = true; + for (const auto &Current : Order) { + if (First) { + First = false; + continue; + } + if (Previous + 1 != Current) + return false; + Previous = Current; + } + return true; + } + +}; + /// This class provides the information for the target register banks. -class AArch64RegisterBankInfo final : public RegisterBankInfo { +class AArch64RegisterBankInfo final : public AArch64GenRegisterBankInfo { /// See RegisterBankInfo::applyMapping. void applyMappingImpl(const OperandsMapper &OpdMapper) const override; |