diff options
author | Kristof Beyls <kristof.beyls@arm.com> | 2017-01-05 10:16:08 +0000 |
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committer | Kristof Beyls <kristof.beyls@arm.com> | 2017-01-05 10:16:08 +0000 |
commit | 44e43a64a6e189325bcc9b2b60ae4d6b56bd6983 (patch) | |
tree | 20f19d7eb086de7203d0ed79a114a424aaaa842a /lib/Target/AArch64/AArch64InstructionSelector.cpp | |
parent | 030c24dcda447bd1aee44897244c7aca1cef2eb1 (diff) |
[GlobalISel] Fix AArch64 ICMP instruction selection
Differential Revision: https://reviews.llvm.org/D28175
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291097 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/AArch64/AArch64InstructionSelector.cpp')
-rw-r--r-- | lib/Target/AArch64/AArch64InstructionSelector.cpp | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/lib/Target/AArch64/AArch64InstructionSelector.cpp b/lib/Target/AArch64/AArch64InstructionSelector.cpp index 20de07424c5..b51473524c7 100644 --- a/lib/Target/AArch64/AArch64InstructionSelector.cpp +++ b/lib/Target/AArch64/AArch64InstructionSelector.cpp @@ -1071,8 +1071,12 @@ bool AArch64InstructionSelector::select(MachineInstr &I) const { return false; } - const AArch64CC::CondCode CC = changeICMPPredToAArch64CC( - (CmpInst::Predicate)I.getOperand(1).getPredicate()); + // CSINC increments the result by one when the condition code is false. + // Therefore, we have to invert the predicate to get an increment by 1 when + // the predicate is true. + const AArch64CC::CondCode invCC = + changeICMPPredToAArch64CC(CmpInst::getInversePredicate( + (CmpInst::Predicate)I.getOperand(1).getPredicate())); MachineInstr &CmpMI = *BuildMI(MBB, I, I.getDebugLoc(), TII.get(CmpOpc)) .addDef(ZReg) @@ -1084,7 +1088,7 @@ bool AArch64InstructionSelector::select(MachineInstr &I) const { .addDef(I.getOperand(0).getReg()) .addUse(AArch64::WZR) .addUse(AArch64::WZR) - .addImm(CC); + .addImm(invCC); constrainSelectedInstRegOperands(CmpMI, TII, TRI, RBI); constrainSelectedInstRegOperands(CSetMI, TII, TRI, RBI); |