diff options
author | Hans Wennborg <hans@hanshq.net> | 2018-02-20 15:49:15 +0000 |
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committer | Hans Wennborg <hans@hanshq.net> | 2018-02-20 15:49:15 +0000 |
commit | b99df1f39716db5a508af88d991fb964fa580751 (patch) | |
tree | 1d83f2f03bbfdd992b7e0c404f8dfb62db8cfcfe /lib/Target/AArch64/AArch64InstructionSelector.cpp | |
parent | 3a4f297d2967b8f86330fb9116229955d6bd6ca1 (diff) |
Merging r325463:
(I had to re-generate the test and manually update to handle the r323922 MIR physical register sigil.
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r325463 | aemerson | 2018-02-18 18:10:49 +0100 (Sun, 18 Feb 2018) | 8 lines
[AArch64][GlobalISel] Fix an assert fail/miscompile when fp16 types are copied
to gpr register banks.
PR36345.
rdar://36478867
Differential Revision: https://reviews.llvm.org/D43310
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@325586 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/AArch64/AArch64InstructionSelector.cpp')
-rw-r--r-- | lib/Target/AArch64/AArch64InstructionSelector.cpp | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/lib/Target/AArch64/AArch64InstructionSelector.cpp b/lib/Target/AArch64/AArch64InstructionSelector.cpp index d60a156666e..a5fe398e7ea 100644 --- a/lib/Target/AArch64/AArch64InstructionSelector.cpp +++ b/lib/Target/AArch64/AArch64InstructionSelector.cpp @@ -354,6 +354,31 @@ static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII, return false; } + if (!TargetRegisterInfo::isPhysicalRegister(SrcReg)) { + const RegClassOrRegBank &RegClassOrBank = + MRI.getRegClassOrRegBank(SrcReg); + + const TargetRegisterClass *SrcRC = + RegClassOrBank.dyn_cast<const TargetRegisterClass *>(); + const RegisterBank *RB = nullptr; + if (!SrcRC) { + RB = RegClassOrBank.get<const RegisterBank *>(); + SrcRC = getRegClassForTypeOnBank(MRI.getType(SrcReg), *RB, RBI, true); + } + // Copies from fpr16 to gpr32 need to use SUBREG_TO_REG. + if (RC == &AArch64::GPR32allRegClass && SrcRC == &AArch64::FPR16RegClass) { + unsigned PromoteReg = MRI.createVirtualRegister(&AArch64::FPR32RegClass); + BuildMI(*I.getParent(), I, I.getDebugLoc(), + TII.get(AArch64::SUBREG_TO_REG)) + .addDef(PromoteReg) + .addImm(0) + .addUse(SrcReg) + .addImm(AArch64::hsub); + MachineOperand &RegOp = I.getOperand(1); + RegOp.setReg(PromoteReg); + } + } + // No need to constrain SrcReg. It will get constrained when // we hit another of its use or its defs. // Copies do not have constraints. |