GlobalISel: split aggregates for PCS lowering

This should match the existing behaviour for passing complicated struct and
array types, in particular HFAs come through like that from Clang.

For C & C++ we still need to somehow support all the weird ABI flags, or at
least those that are present in the IR (signext, byval, ...), and stack-based
parameter passing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281977 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 10 insertions, 2 deletions

diff --git a/lib/Target/AArch64/AArch64CallLowering.h b/lib/Target/AArch64/AArch64CallLowering.h
index 1588ad44ad7..05b415fd45e 100644
--- a/lib/Target/AArch64/AArch64CallLowering.h
+++ b/lib/Target/AArch64/AArch64CallLowering.h
@@ -35,14 +35,22 @@ class AArch64CallLowering: public CallLowering {
                             ArrayRef<unsigned> VRegs) const override;
 
   bool lowerCall(MachineIRBuilder &MIRBuilder, const MachineOperand &Callee,
-                 ArrayRef<Type *> ResTys, ArrayRef<unsigned> ResRegs,
-                 ArrayRef<Type *> ArgTys,
+                 Type *ResTy, unsigned ResReg, ArrayRef<Type *> ArgTys,
                  ArrayRef<unsigned> ArgRegs) const override;
 
 private:
   typedef std::function<void(MachineIRBuilder &, Type *, unsigned, unsigned)>
       AssignFnTy;
 
+  typedef std::function<void(ArrayRef<unsigned>, ArrayRef<uint64_t>)>
+      SplitArgTy;
+
+  void splitToValueTypes(unsigned Reg, Type *Ty,
+                         SmallVectorImpl<unsigned> &SplitRegs,
+                         SmallVectorImpl<Type *> &SplitTys,
+                         const DataLayout &DL, MachineRegisterInfo &MRI,
+                         SplitArgTy SplitArg) const;
+
   bool handleAssignments(MachineIRBuilder &MIRBuilder, CCAssignFn *AssignFn,
                          ArrayRef<Type *> ArgsTypes, ArrayRef<unsigned> ArgRegs,
                          AssignFnTy AssignValToReg) const;