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authorNirav Dave <niravd@google.com>2017-12-22 22:06:56 +0000
committerNirav Dave <niravd@google.com>2017-12-22 22:06:56 +0000
commite1b8f14c6dd0b254a547f03a5dfd6fee6249f847 (patch)
treefa9c5aa45b62c80f852a9dde4e4fb81ec64f215f /lib/CodeGen
parent5d9f5f40885da16ed6f4e9ee7c96a3547500d900 (diff)
[DAG] Add missing case check from findbaseoffset merge from r321389.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321391 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen')
-rw-r--r--lib/CodeGen/SelectionDAG/DAGCombiner.cpp6
1 files changed, 4 insertions, 2 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 5bab282cb09..99c450e612b 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -17453,8 +17453,10 @@ bool DAGCombiner::isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1) const {
bool IsCV0 = isa<ConstantPoolSDNode>(BasePtr0.getBase());
bool IsCV1 = isa<ConstantPoolSDNode>(BasePtr1.getBase());
- // If of mismatched base types they do not alias.
- if (((IsFI0 != IsFI1) || (IsGV0 != IsGV1) || (IsCV0 != IsCV1)) &&
+ // If of mismatched base types or checkable indices we can check
+ // they do not alias.
+ if ((BasePtr0.getIndex() == BasePtr1.getIndex() || (IsFI0 != IsFI1) ||
+ (IsGV0 != IsGV1) || (IsCV0 != IsCV1)) &&
(IsFI0 || IsGV0 || IsCV0) && (IsFI1 || IsGV1 || IsCV1))
return false;