diff options
| author | Francis Visoiu Mistrih <francisvm@yahoo.com> | 2017-11-28 17:15:09 +0000 |
|---|---|---|
| committer | Francis Visoiu Mistrih <francisvm@yahoo.com> | 2017-11-28 17:15:09 +0000 |
| commit | a4ec08b6fd62577a5c0e9ddd3c131e223c0672b8 (patch) | |
| tree | 14dc42e84a489e5ec4e9aefdf9e086ab70c1427d /lib/CodeGen/TwoAddressInstructionPass.cpp | |
| parent | 7005517f42852ddb80ca986a2933f729d4fd0383 (diff) | |
[CodeGen] Print register names in lowercase in both MIR and debug output
As part of the unification of the debug format and the MIR format,
always print registers as lowercase.
* Only debug printing is affected. It now follows MIR.
Differential Revision: https://reviews.llvm.org/D40417
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319187 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/TwoAddressInstructionPass.cpp')
| -rw-r--r-- | lib/CodeGen/TwoAddressInstructionPass.cpp | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/lib/CodeGen/TwoAddressInstructionPass.cpp b/lib/CodeGen/TwoAddressInstructionPass.cpp index 650912f56a3..b996850d706 100644 --- a/lib/CodeGen/TwoAddressInstructionPass.cpp +++ b/lib/CodeGen/TwoAddressInstructionPass.cpp @@ -589,23 +589,23 @@ isProfitableToCommute(unsigned regA, unsigned regB, unsigned regC, // e.g. // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1 // %reg1029<def> = MOV8rr %reg1028 - // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead> + // %reg1029<def> = SHR8ri %reg1029, 7, %eflags<imp-def,dead> // insert => %reg1030<def> = MOV8rr %reg1028 - // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead> + // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %eflags<imp-def,dead> // In this case, it might not be possible to coalesce the second MOV8rr // instruction if the first one is coalesced. So it would be profitable to // commute it: // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1 // %reg1029<def> = MOV8rr %reg1028 - // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead> + // %reg1029<def> = SHR8ri %reg1029, 7, %eflags<imp-def,dead> // insert => %reg1030<def> = MOV8rr %reg1029 - // %reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead> + // %reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %eflags<imp-def,dead> if (!isPlainlyKilled(MI, regC, LIS)) return false; // Ok, we have something like: - // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead> + // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %eflags<imp-def,dead> // let's see if it's worth commuting it. // Look for situations like this: |