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| author | Francis Visoiu Mistrih <fvisoiumistrih@apple.com> | 2017-05-17 01:07:53 +0000 |
|---|---|---|
| committer | Francis Visoiu Mistrih <fvisoiumistrih@apple.com> | 2017-05-17 01:07:53 +0000 |
| commit | 1179b5ee404e109ee706364ca4ac89e28443f9cf (patch) | |
| tree | 2426c3a027d856213bf6eadd306cf0121f11c8c5 /lib/CodeGen/TargetLoweringBase.cpp | |
| parent | 6f42331357504f6cd7765b56cccd49c5a3cc4166 (diff) | |
BitVector: add iterators for set bits
Differential revision: https://reviews.llvm.org/D32060
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303227 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/TargetLoweringBase.cpp')
| -rw-r--r-- | lib/CodeGen/TargetLoweringBase.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/CodeGen/TargetLoweringBase.cpp b/lib/CodeGen/TargetLoweringBase.cpp index 39aa946fa84..5f63fd4320b 100644 --- a/lib/CodeGen/TargetLoweringBase.cpp +++ b/lib/CodeGen/TargetLoweringBase.cpp @@ -1312,7 +1312,7 @@ TargetLoweringBase::findRepresentativeClass(const TargetRegisterInfo *TRI, // Find the first legal register class with the largest spill size. const TargetRegisterClass *BestRC = RC; - for (int i = SuperRegRC.find_first(); i >= 0; i = SuperRegRC.find_next(i)) { + for (unsigned i : SuperRegRC.set_bits()) { const TargetRegisterClass *SuperRC = TRI->getRegClass(i); // We want the largest possible spill size. if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC)) |