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authorMatthias Braun <matze@braunis.de>2016-11-11 22:37:31 +0000
committerMatthias Braun <matze@braunis.de>2016-11-11 22:37:31 +0000
commit97c4b7addd559830a25f52774fe477089f329688 (patch)
tree94cf735b733147ca00b80d076a6bd298bb922b6c /lib/CodeGen/ScheduleDAGInstrs.cpp
parente9923d3f0ae504d349398c80ea01017188476f29 (diff)
ScheduleDAGInstrs: Move VRegUses to ScheduleDAGMILive; NFCI
Push VRegUses/collectVRegUses() down the class hierarchy towards its only user ScheduleDAGMILive. NFCI: The initialization of the map happens at a later point but that should not matter. This is in preparation to allow DAG mutators to merge nodes, which relies on this map getting computed later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286654 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/ScheduleDAGInstrs.cpp')
-rw-r--r--lib/CodeGen/ScheduleDAGInstrs.cpp43
1 files changed, 0 insertions, 43 deletions
diff --git a/lib/CodeGen/ScheduleDAGInstrs.cpp b/lib/CodeGen/ScheduleDAGInstrs.cpp
index 02461976177..510716e8a77 100644
--- a/lib/CodeGen/ScheduleDAGInstrs.cpp
+++ b/lib/CodeGen/ScheduleDAGInstrs.cpp
@@ -680,44 +680,6 @@ void ScheduleDAGInstrs::initSUnits() {
}
}
-void ScheduleDAGInstrs::collectVRegUses(SUnit *SU) {
- const MachineInstr *MI = SU->getInstr();
- for (const MachineOperand &MO : MI->operands()) {
- if (!MO.isReg())
- continue;
- if (!MO.readsReg())
- continue;
- if (TrackLaneMasks && !MO.isUse())
- continue;
-
- unsigned Reg = MO.getReg();
- if (!TargetRegisterInfo::isVirtualRegister(Reg))
- continue;
-
- // Ignore re-defs.
- if (TrackLaneMasks) {
- bool FoundDef = false;
- for (const MachineOperand &MO2 : MI->operands()) {
- if (MO2.isReg() && MO2.isDef() && MO2.getReg() == Reg && !MO2.isDead()) {
- FoundDef = true;
- break;
- }
- }
- if (FoundDef)
- continue;
- }
-
- // Record this local VReg use.
- VReg2SUnitMultiMap::iterator UI = VRegUses.find(Reg);
- for (; UI != VRegUses.end(); ++UI) {
- if (UI->SU == SU)
- break;
- }
- if (UI == VRegUses.end())
- VRegUses.insert(VReg2SUnit(Reg, 0, SU));
- }
-}
-
class ScheduleDAGInstrs::Value2SUsMap : public MapVector<ValueType, SUList> {
/// Current total number of SUs in map.
@@ -895,9 +857,6 @@ void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA,
CurrentVRegDefs.setUniverse(NumVirtRegs);
CurrentVRegUses.setUniverse(NumVirtRegs);
- VRegUses.clear();
- VRegUses.setUniverse(NumVirtRegs);
-
// Model data dependencies between instructions being scheduled and the
// ExitSU.
addSchedBarrierDeps();
@@ -920,8 +879,6 @@ void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA,
assert(SU && "No SUnit mapped to this MI");
if (RPTracker) {
- collectVRegUses(SU);
-
RegisterOperands RegOpers;
RegOpers.collect(MI, *TRI, MRI, TrackLaneMasks, false);
if (TrackLaneMasks) {