[Pipeliner] Fix offset value for instrs dependent on post-inc load/stores

The software pipeliner and the packetizer try to break dependence
between the post-increment instruction and the dependent memory
instructions by changing the base register and the offset value.
However, in some cases, the existing logic didn't work properly
and created incorrect offset value.

Patch by Jyotsna Verma.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315468 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 8 insertions, 3 deletions

diff --git a/lib/CodeGen/MachinePipeliner.cpp b/lib/CodeGen/MachinePipeliner.cpp
index 20141f7f8d6..c852c2e1564 100644
--- a/lib/CodeGen/MachinePipeliner.cpp
+++ b/lib/CodeGen/MachinePipeliner.cpp
@@ -3892,9 +3892,14 @@ void SwingSchedulerDAG::fixupRegisterOverlaps(std::deque<SUnit *> &Instrs) {
           unsigned BasePos, OffsetPos;
           // Update the base register and adjust the offset.
           if (TII->getBaseAndOffsetPosition(*MI, BasePos, OffsetPos)) {
-            MI->getOperand(BasePos).setReg(NewBaseReg);
-            int64_t Offset = MI->getOperand(OffsetPos).getImm();
-            MI->getOperand(OffsetPos).setImm(Offset - It->second.second);
+            MachineInstr *NewMI = MF.CloneMachineInstr(MI);
+            NewMI->getOperand(BasePos).setReg(NewBaseReg);
+            int64_t NewOffset =
+                MI->getOperand(OffsetPos).getImm() - It->second.second;
+            NewMI->getOperand(OffsetPos).setImm(NewOffset);
+            SU->setInstr(NewMI);
+            MISUnitMap[NewMI] = SU;
+            NewMIs.insert(NewMI);
           }
         }
         OverlapReg = 0;