[CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312971 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 50 insertions, 49 deletions

diff --git a/lib/CodeGen/MachinePipeliner.cpp b/lib/CodeGen/MachinePipeliner.cpp
index 94ab062091e..91e1257ba4d 100644
--- a/lib/CodeGen/MachinePipeliner.cpp
+++ b/lib/CodeGen/MachinePipeliner.cpp
@@ -1,4 +1,4 @@
-//===-- MachinePipeliner.cpp - Machine Software Pipeliner Pass ------------===//
+//===- MachinePipeliner.cpp - Machine Software Pipeliner Pass -------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -80,7 +80,6 @@
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/CodeGen/MachineInstrBundle.h"
 #include "llvm/CodeGen/MachineLoopInfo.h"
 #include "llvm/CodeGen/MachineMemOperand.h"
 #include "llvm/CodeGen/MachineOperand.h"
@@ -92,15 +91,19 @@
 #include "llvm/CodeGen/ScheduleDAGMutation.h"
 #include "llvm/IR/Attributes.h"
 #include "llvm/IR/DebugLoc.h"
+#include "llvm/IR/Function.h"
+#include "llvm/MC/LaneBitmask.h"
+#include "llvm/MC/MCInstrDesc.h"
 #include "llvm/MC/MCInstrItineraries.h"
-#include "llvm/PassAnalysisSupport.h"
-#include "llvm/PassRegistry.h"
-#include "llvm/PassSupport.h"
+#include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/Pass.h"
 #include "llvm/Support/CommandLine.h"
+#include "llvm/Support/Compiler.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/Target/TargetOpcodes.h"
 #include "llvm/Target/TargetRegisterInfo.h"
 #include "llvm/Target/TargetSubtargetInfo.h"
 #include <algorithm>
@@ -111,6 +114,7 @@
 #include <functional>
 #include <iterator>
 #include <map>
+#include <memory>
 #include <tuple>
 #include <utility>
 #include <vector>
@@ -169,7 +173,6 @@ namespace {
 
 class NodeSet;
 class SMSchedule;
-class SwingSchedulerDAG;
 
 /// The main class in the implementation of the target independent
 /// software pipeliner pass.
@@ -185,6 +188,7 @@ public:
 #ifndef NDEBUG
   static int NumTries;
 #endif
+
   /// Cache the target analysis information about the loop.
   struct LoopInfo {
     MachineBasicBlock *TBB = nullptr;
@@ -196,6 +200,7 @@ public:
   LoopInfo LI;
 
   static char ID;
+
   MachinePipeliner() : MachineFunctionPass(ID) {
     initializeMachinePipelinerPass(*PassRegistry::getPassRegistry());
   }
@@ -222,9 +227,9 @@ private:
 class SwingSchedulerDAG : public ScheduleDAGInstrs {
   MachinePipeliner &Pass;
   /// The minimum initiation interval between iterations for this schedule.
-  unsigned MII;
+  unsigned MII = 0;
   /// Set to true if a valid pipelined schedule is found for the loop.
-  bool Scheduled;
+  bool Scheduled = false;
   MachineLoop &Loop;
   LiveIntervals &LIS;
   const RegisterClassInfo &RegClassInfo;
@@ -234,9 +239,10 @@ class SwingSchedulerDAG : public ScheduleDAGInstrs {
   ScheduleDAGTopologicalSort Topo;
 
   struct NodeInfo {
-    int ASAP;
-    int ALAP;
-    NodeInfo() : ASAP(0), ALAP(0) {}
+    int ASAP = 0;
+    int ALAP = 0;
+
+    NodeInfo() = default;
   };
   /// Computed properties for each node in the graph.
   std::vector<NodeInfo> ScheduleInfo;
@@ -245,10 +251,10 @@ class SwingSchedulerDAG : public ScheduleDAGInstrs {
   /// Computed node ordering for scheduling.
   SetVector<SUnit *> NodeOrder;
 
-  typedef SmallVector<NodeSet, 8> NodeSetType;
-  typedef DenseMap<unsigned, unsigned> ValueMapTy;
-  typedef SmallVectorImpl<MachineBasicBlock *> MBBVectorTy;
-  typedef DenseMap<MachineInstr *, MachineInstr *> InstrMapTy;
+  using NodeSetType = SmallVector<NodeSet, 8>;
+  using ValueMapTy = DenseMap<unsigned, unsigned>;
+  using MBBVectorTy = SmallVectorImpl<MachineBasicBlock *>;
+  using InstrMapTy = DenseMap<MachineInstr *, MachineInstr *>;
 
   /// Instructions to change when emitting the final schedule.
   DenseMap<SUnit *, std::pair<unsigned, int64_t>> InstrChanges;
@@ -272,8 +278,8 @@ class SwingSchedulerDAG : public ScheduleDAGInstrs {
 
   public:
     Circuits(std::vector<SUnit> &SUs)
-        : SUnits(SUs), Stack(), Blocked(SUs.size()), B(SUs.size()),
-          AdjK(SUs.size()) {}
+        : SUnits(SUs), Blocked(SUs.size()), B(SUs.size()), AdjK(SUs.size()) {}
+
     /// Reset the data structures used in the circuit algorithm.
     void reset() {
       Stack.clear();
@@ -281,6 +287,7 @@ class SwingSchedulerDAG : public ScheduleDAGInstrs {
       B.assign(SUnits.size(), SmallPtrSet<SUnit *, 4>());
       NumPaths = 0;
     }
+
     void createAdjacencyStructure(SwingSchedulerDAG *DAG);
     bool circuit(int V, int S, NodeSetType &NodeSets, bool HasBackedge = false);
     void unblock(int U);
@@ -289,9 +296,8 @@ class SwingSchedulerDAG : public ScheduleDAGInstrs {
 public:
   SwingSchedulerDAG(MachinePipeliner &P, MachineLoop &L, LiveIntervals &lis,
                     const RegisterClassInfo &rci)
-      : ScheduleDAGInstrs(*P.MF, P.MLI, false), Pass(P), MII(0),
-        Scheduled(false), Loop(L), LIS(lis), RegClassInfo(rci),
-        Topo(SUnits, &ExitSU) {
+      : ScheduleDAGInstrs(*P.MF, P.MLI, false), Pass(P), Loop(L), LIS(lis),
+        RegClassInfo(rci), Topo(SUnits, &ExitSU) {
     P.MF->getSubtarget().getSMSMutations(Mutations);
   }
 
@@ -455,7 +461,7 @@ private:
 /// that assigns a priority to the set.
 class NodeSet {
   SetVector<SUnit *> Nodes;
-  bool HasRecurrence;
+  bool HasRecurrence = false;
   unsigned RecMII = 0;
   int MaxMOV = 0;
   int MaxDepth = 0;
@@ -463,10 +469,9 @@ class NodeSet {
   SUnit *ExceedPressure = nullptr;
 
 public:
-  typedef SetVector<SUnit *>::const_iterator iterator;
-
-  NodeSet() : Nodes(), HasRecurrence(false) {}
+  using iterator = SetVector<SUnit *>::const_iterator;
 
+  NodeSet() = default;
   NodeSet(iterator S, iterator E) : Nodes(S, E), HasRecurrence(true) {}
 
   bool insert(SUnit *SU) { return Nodes.insert(SU); }
@@ -581,13 +586,13 @@ private:
 
   /// Keep track of the first cycle value in the schedule.  It starts
   /// as zero, but the algorithm allows negative values.
-  int FirstCycle;
+  int FirstCycle = 0;
 
   /// Keep track of the last cycle value in the schedule.
-  int LastCycle;
+  int LastCycle = 0;
 
   /// The initiation interval (II) for the schedule.
-  int InitiationInterval;
+  int InitiationInterval = 0;
 
   /// Target machine information.
   const TargetSubtargetInfo &ST;
@@ -600,11 +605,7 @@ private:
 public:
   SMSchedule(MachineFunction *mf)
       : ST(mf->getSubtarget()), MRI(mf->getRegInfo()),
-        Resources(ST.getInstrInfo()->CreateTargetScheduleState(ST)) {
-    FirstCycle = 0;
-    LastCycle = 0;
-    InitiationInterval = 0;
-  }
+        Resources(ST.getInstrInfo()->CreateTargetScheduleState(ST)) {}
 
   void reset() {
     ScheduledInstrs.clear();
@@ -638,9 +639,9 @@ public:
   bool insert(SUnit *SU, int StartCycle, int EndCycle, int II);
 
   /// Iterators for the cycle to instruction map.
-  typedef DenseMap<int, std::deque<SUnit *>>::iterator sched_iterator;
-  typedef DenseMap<int, std::deque<SUnit *>>::const_iterator
-      const_sched_iterator;
+  using sched_iterator = DenseMap<int, std::deque<SUnit *>>::iterator;
+  using const_sched_iterator =
+      DenseMap<int, std::deque<SUnit *>>::const_iterator;
 
   /// Return true if the instruction is scheduled at the specified stage.
   bool isScheduledAtStage(SUnit *SU, unsigned StageNum) {
@@ -715,6 +716,7 @@ char MachinePipeliner::ID = 0;
 int MachinePipeliner::NumTries = 0;
 #endif
 char &llvm::MachinePipelinerID = MachinePipeliner::ID;
+
 INITIALIZE_PASS_BEGIN(MachinePipeliner, DEBUG_TYPE,
                       "Modulo Software Pipelining", false, false)
 INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
@@ -1256,6 +1258,8 @@ struct FuncUnitSorter {
   const InstrItineraryData *InstrItins;
   DenseMap<unsigned, unsigned> Resources;
 
+  FuncUnitSorter(const InstrItineraryData *IID) : InstrItins(IID) {}
+
   // Compute the number of functional unit alternatives needed
   // at each stage, and take the minimum value. We prioritize the
   // instructions by the least number of choices first.
@@ -1291,7 +1295,6 @@ struct FuncUnitSorter {
     }
   }
 
-  FuncUnitSorter(const InstrItineraryData *IID) : InstrItins(IID) {}
   /// Return true if IS1 has less priority than IS2.
   bool operator()(const MachineInstr *IS1, const MachineInstr *IS2) const {
     unsigned F1 = 0, F2 = 0;
@@ -1384,7 +1387,7 @@ unsigned SwingSchedulerDAG::calculateRecMII(NodeSetType &NodeSets) {
   unsigned RecMII = 0;
 
   for (NodeSet &Nodes : NodeSets) {
-    if (Nodes.size() == 0)
+    if (Nodes.empty())
       continue;
 
     unsigned Delay = Nodes.size() - 1;
@@ -1554,7 +1557,6 @@ static bool ignoreDependence(const SDep &D, bool isPred) {
 ///  D - Depth of each node.
 ///  H - Height of each node.
 void SwingSchedulerDAG::computeNodeFunctions(NodeSetType &NodeSets) {
-
   ScheduleInfo.resize(SUnits.size());
 
   DEBUG({
@@ -1651,7 +1653,7 @@ static bool pred_L(SetVector<SUnit *> &NodeOrder,
         Preds.insert(IS->getSUnit());
     }
   }
-  return Preds.size() > 0;
+  return !Preds.empty();
 }
 
 /// Compute the Succ_L(O) set, as defined in the paper. The set is defined
@@ -1683,7 +1685,7 @@ static bool succ_L(SetVector<SUnit *> &NodeOrder,
         Succs.insert(PI->getSUnit());
     }
   }
-  return Succs.size() > 0;
+  return !Succs.empty();
 }
 
 /// Return true if there is a path from the specified node to any of the nodes
@@ -1868,7 +1870,7 @@ void SwingSchedulerDAG::groupRemainingNodes(NodeSetType &NodeSets) {
         Visited.clear();
         computePath(NI, Path, NodesAdded, I, Visited);
       }
-      if (Path.size() > 0)
+      if (!Path.empty())
         I.insert(Path.begin(), Path.end());
     }
     // Add the nodes from the previous node set to the current node set.
@@ -1879,7 +1881,7 @@ void SwingSchedulerDAG::groupRemainingNodes(NodeSetType &NodeSets) {
         Visited.clear();
         computePath(NI, Path, I, NodesAdded, Visited);
       }
-      if (Path.size() > 0)
+      if (!Path.empty())
         I.insert(Path.begin(), Path.end());
     }
     NodesAdded.insert(I.begin(), I.end());
@@ -1892,7 +1894,7 @@ void SwingSchedulerDAG::groupRemainingNodes(NodeSetType &NodeSets) {
   if (succ_L(NodesAdded, N))
     for (SUnit *I : N)
       addConnectedNodes(I, NewSet, NodesAdded);
-  if (NewSet.size() > 0)
+  if (!NewSet.empty())
     NodeSets.push_back(NewSet);
 
   // Create a new node set with the connected nodes of any predecessor of a node
@@ -1901,7 +1903,7 @@ void SwingSchedulerDAG::groupRemainingNodes(NodeSetType &NodeSets) {
   if (pred_L(NodesAdded, N))
     for (SUnit *I : N)
       addConnectedNodes(I, NewSet, NodesAdded);
-  if (NewSet.size() > 0)
+  if (!NewSet.empty())
     NodeSets.push_back(NewSet);
 
   // Create new nodes sets with the connected nodes any any remaining node that
@@ -1911,7 +1913,7 @@ void SwingSchedulerDAG::groupRemainingNodes(NodeSetType &NodeSets) {
     if (NodesAdded.count(SU) == 0) {
       NewSet.clear();
       addConnectedNodes(SU, NewSet, NodesAdded);
-      if (NewSet.size() > 0)
+      if (!NewSet.empty())
         NodeSets.push_back(NewSet);
     }
   }
@@ -1976,7 +1978,7 @@ void SwingSchedulerDAG::removeDuplicateNodes(NodeSetType &NodeSets) {
     for (NodeSetType::iterator J = I + 1; J != E;) {
       J->remove_if([&](SUnit *SUJ) { return I->count(SUJ); });
 
-      if (J->size() == 0) {
+      if (J->empty()) {
         NodeSets.erase(J);
         E = NodeSets.end();
       } else {
@@ -2147,8 +2149,7 @@ void SwingSchedulerDAG::computeNodeOrder(NodeSetType &NodeSets) {
 /// Process the nodes in the computed order and create the pipelined schedule
 /// of the instructions, if possible. Return true if a schedule is found.
 bool SwingSchedulerDAG::schedulePipeline(SMSchedule &Schedule) {
-
-  if (NodeOrder.size() == 0)
+  if (NodeOrder.empty())
     return false;
 
   bool scheduleFound = false;
@@ -2325,7 +2326,7 @@ void SwingSchedulerDAG::generateProlog(SMSchedule &Schedule, unsigned LastStage,
                                        ValueMapTy *VRMap,
                                        MBBVectorTy &PrologBBs) {
   MachineBasicBlock *PreheaderBB = MLI->getLoopFor(BB)->getLoopPreheader();
-  assert(PreheaderBB != NULL &&
+  assert(PreheaderBB != nullptr &&
          "Need to add code to handle loops w/o preheader");
   MachineBasicBlock *PredBB = PreheaderBB;
   InstrMapTy InstrMap;