diff options
author | Hiroshi Inoue <inouehrs@jp.ibm.com> | 2018-06-20 05:29:26 +0000 |
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committer | Hiroshi Inoue <inouehrs@jp.ibm.com> | 2018-06-20 05:29:26 +0000 |
commit | 73d058aa97f93df272a8fdb4037da8325f9b14d7 (patch) | |
tree | 830c4d1f9099e28fe1d4b51e0d448ab31585347a /lib/CodeGen/MachinePipeliner.cpp | |
parent | 09d5b89fff4dfbac9799217d547e6bae6e1be88c (diff) |
[NFC] fix trivial typos in comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335096 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/MachinePipeliner.cpp')
-rw-r--r-- | lib/CodeGen/MachinePipeliner.cpp | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/lib/CodeGen/MachinePipeliner.cpp b/lib/CodeGen/MachinePipeliner.cpp index ef96cec4f97..5e1760ef808 100644 --- a/lib/CodeGen/MachinePipeliner.cpp +++ b/lib/CodeGen/MachinePipeliner.cpp @@ -17,7 +17,7 @@ // interval, register requirements, and stage count. See the papers: // // "Swing Modulo Scheduling: A Lifetime-Sensitive Approach", by J. Llosa, -// A. Gonzalez, E. Ayguade, and M. Valero. In PACT '96 Processings of the 1996 +// A. Gonzalez, E. Ayguade, and M. Valero. In PACT '96 Proceedings of the 1996 // Conference on Parallel Architectures and Compilation Techiniques. // // "Lifetime-Sensitive Modulo Scheduling in a Production Environment", by J. @@ -570,7 +570,7 @@ public: #endif }; -/// This class repesents the scheduled code. The main data structure is a +/// This class represents the scheduled code. The main data structure is a /// map from scheduled cycle to instructions. During scheduling, the /// data structure explicitly represents all stages/iterations. When /// the algorithm finshes, the schedule is collapsed into a single stage, @@ -1437,7 +1437,7 @@ unsigned SwingSchedulerDAG::calculateResMII() { /// Iterate over each circuit. Compute the delay(c) and distance(c) /// for each circuit. The II needs to satisfy the inequality /// delay(c) - II*distance(c) <= 0. For each circuit, choose the smallest -/// II that satistifies the inequality, and the RecMII is the maximum +/// II that satisfies the inequality, and the RecMII is the maximum /// of those values. unsigned SwingSchedulerDAG::calculateRecMII(NodeSetType &NodeSets) { unsigned RecMII = 0; @@ -1617,7 +1617,7 @@ void SwingSchedulerDAG::findCircuits(NodeSetType &NodeSets) { } /// Return true for DAG nodes that we ignore when computing the cost functions. -/// We ignore the back-edge recurrence in order to avoid unbounded recurison +/// We ignore the back-edge recurrence in order to avoid unbounded recursion /// in the calculation of the ASAP, ALAP, etc functions. static bool ignoreDependence(const SDep &D, bool isPred) { if (D.isArtificial()) @@ -2330,7 +2330,7 @@ void SwingSchedulerDAG::generatePipelinedLoop(SMSchedule &Schedule) { // Remember the registers that are used in different stages. The index is // the iteration, or stage, that the instruction is scheduled in. This is - // a map between register names in the orignal block and the names created + // a map between register names in the original block and the names created // in each stage of the pipelined loop. ValueMapTy *VRMap = new ValueMapTy[(MaxStageCount + 1) * 2]; InstrMapTy InstrMap; @@ -2825,7 +2825,7 @@ void SwingSchedulerDAG::generateExistingPhis( /// Generate Phis for the specified block in the generated pipelined code. /// These are new Phis needed because the definition is scheduled after the -/// use in the pipelened sequence. +/// use in the pipelined sequence. void SwingSchedulerDAG::generatePhis( MachineBasicBlock *NewBB, MachineBasicBlock *BB1, MachineBasicBlock *BB2, MachineBasicBlock *KernelBB, SMSchedule &Schedule, ValueMapTy *VRMap, @@ -3711,7 +3711,7 @@ void SMSchedule::computeStart(SUnit *SU, int *MaxEarlyStart, int *MinLateStart, int *MinEnd, int *MaxStart, int II, SwingSchedulerDAG *DAG) { // Iterate over each instruction that has been scheduled already. The start - // slot computuation depends on whether the previously scheduled instruction + // slot computation depends on whether the previously scheduled instruction // is a predecessor or successor of the specified instruction. for (int cycle = getFirstCycle(); cycle <= LastCycle; ++cycle) { @@ -3892,7 +3892,7 @@ void SMSchedule::orderDependence(SwingSchedulerDAG *SSD, SUnit *SU, bool SMSchedule::isLoopCarried(SwingSchedulerDAG *SSD, MachineInstr &Phi) { if (!Phi.isPHI()) return false; - assert(Phi.isPHI() && "Expecing a Phi."); + assert(Phi.isPHI() && "Expecting a Phi."); SUnit *DefSU = SSD->getSUnit(&Phi); unsigned DefCycle = cycleScheduled(DefSU); int DefStage = stageScheduled(DefSU); |