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author | Chris Lattner <sabre@nondot.org> | 2010-11-06 08:30:26 +0000 |
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committer | Chris Lattner <sabre@nondot.org> | 2010-11-06 08:30:26 +0000 |
commit | c7a03fbe66116929fab679a34748e1bf552de879 (patch) | |
tree | b7907523da787e4531866b4e6d208e0e7372bb44 /docs | |
parent | 5bde7345980587284bda6d42a68cdb151fbf5d6b (diff) |
document instalias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118335 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'docs')
-rw-r--r-- | docs/CodeGenerator.html | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/docs/CodeGenerator.html b/docs/CodeGenerator.html index f83d7b0e313..d4e932a969f 100644 --- a/docs/CodeGenerator.html +++ b/docs/CodeGenerator.html @@ -1957,6 +1957,55 @@ on the current instruction set.</p> </div> +<!-- _______________________________________________________________________ --> +<div class="doc_subsubsection">Instruction Aliases</div> + +<div class="doc_text"> + +<p>The most general phase of alias processing occurs while matching is +happening: it provides new forms for the matcher to match along with a specific +instruction to generate. An instruction alias has two parts: the string to +match and the instruction to generate. For example: +</p> + +<div class="doc_code"> +<pre> +def : InstAlias<"movsx $src, $dst", (MOVSX16rr8W GR16:$dst, GR8 :$src)>; +def : InstAlias<"movsx $src, $dst", (MOVSX16rm8W GR16:$dst, i8mem:$src)>; +def : InstAlias<"movsx $src, $dst", (MOVSX32rr8 GR32:$dst, GR8 :$src)>; +def : InstAlias<"movsx $src, $dst", (MOVSX32rr16 GR32:$dst, GR16 :$src)>; +def : InstAlias<"movsx $src, $dst", (MOVSX64rr8 GR64:$dst, GR8 :$src)>; +def : InstAlias<"movsx $src, $dst", (MOVSX64rr16 GR64:$dst, GR16 :$src)>; +def : InstAlias<"movsx $src, $dst", (MOVSX64rr32 GR64:$dst, GR32 :$src)>; +</pre> +</div> + +<p>This shows a powerful example of the instruction aliases, matching the +same mnemonic in multiple different ways depending on what operands are present +in the assembly. The result of instruction aliases can include operands in a +different order than the destination instruction, and can use an input +multiple times, for example:</p> + +<div class="doc_code"> +<pre> +def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg)>; +def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg)>; +def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg)>; +def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg)>; +</pre> +</div> + +<p>This example also shows that tied operands are only listed once. In the X86 +backend, XOR8rr has two input GR8's and one output GR8 (where an input is tied +to the output). InstAliases take a flattened operand list without duplicates +for tied operands.</p> + +<p>Instruction aliases can also have a Requires clause to make them +subtarget specific.</p> + +</div> + + <!-- ======================================================================= --> <div class="doc_subsection" id="na_matching">Instruction Matching</div> |