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| author | Tony Tye <Tony.Tye@amd.com> | 2017-06-07 00:08:35 +0000 |
|---|---|---|
| committer | Tony Tye <Tony.Tye@amd.com> | 2017-06-07 00:08:35 +0000 |
| commit | 61c7e03d0a859ba45726087e0d54e2f49f85d3ab (patch) | |
| tree | df2413b07dedb777b985bceab874d8fe22ac9c17 /docs | |
| parent | 2f4ae78089d093fcb36b8fb98e1cfe249e5c9222 (diff) | |
Add documentation for various aspects of the AMDGPU backend.
Remove extra tabs.
Builds sucessfully with Sphinx v1.5.5
Differential Revision: https://reviews.llvm.org/D33736
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304848 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'docs')
| -rw-r--r-- | docs/AMDGPUUsage.rst | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/docs/AMDGPUUsage.rst b/docs/AMDGPUUsage.rst index c8b4072661e..f6dcfc6b579 100644 --- a/docs/AMDGPUUsage.rst +++ b/docs/AMDGPUUsage.rst @@ -2549,7 +2549,7 @@ coherent) and so the L2 cache will coherent with the CPU and other agents. always generate (see comment for previous fence). - - Could be split into + - Could be split into separate s_waitcnt vmcnt(0) and s_waitcnt |