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| author | Craig Topper <craig.topper@intel.com> | 2018-02-23 18:33:04 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-02-23 18:33:04 +0000 |
| commit | 16ebb58ea40d384e8daa4c48d2bf7dd1ccfa5fcd (patch) | |
| tree | 0824dfdd9ccd1d6045671405774d04c7c5156c44 /docs | |
| parent | 72d068a93fe1cd266b091afb9d257b27a18e9be1 (diff) | |
[ReleaseNotes] More X86 updates
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@325932 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'docs')
| -rw-r--r-- | docs/ReleaseNotes.rst | 22 |
1 files changed, 21 insertions, 1 deletions
diff --git a/docs/ReleaseNotes.rst b/docs/ReleaseNotes.rst index 91e7dbb1adf..f2bbdc871ad 100644 --- a/docs/ReleaseNotes.rst +++ b/docs/ReleaseNotes.rst @@ -178,14 +178,34 @@ During this release the X86 target has: * Added support for Intel Icelake CPU. +* Fixed some X87 codegen bugs. + * Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs. -* Improved codegen of data being transferred between GPRs and K-registers. +* Improved scheduler model for AMD Jaguar CPUs. * Improved llvm-mc's disassembler for some EVEX encoded instructions. +* Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions. + +* Improved codegen for memory comparisons + +* Improved codegen for i32 vector multiplies + +* Improved codegen for scalar integer absolute values + +* Improved codegen for vector integer rotations (XOP and AVX512) + +* Improved codegen of data being transferred between GPRs and K-registers. + * Improved codegen for vector truncations. +* Improved folding of address computations into gather/scatter instructions. + +* Gained initial support recognizing variable shuffles from vector element extracts and inserts. + +* Improved documentation for SSE/AVX intrinsics in *intrin.h header files. + Changes to the AMDGPU Target ----------------------------- |