diff options
| author | Alex Bradbury <asb@lowrisc.org> | 2016-11-01 17:27:54 +0000 |
|---|---|---|
| committer | Alex Bradbury <asb@lowrisc.org> | 2016-11-01 17:27:54 +0000 |
| commit | 0ba26af40d2d9582dd8ed42a2d97908207728d59 (patch) | |
| tree | e1b148fdfa4601d4b05f2eca3e7fbf2c2f7e3eff /docs/CompilerWriterInfo.rst | |
| parent | 5216ee3a5fc4b203ef7f54a34249e18caf5a7d62 (diff) | |
[RISCV] Add stub backend
This contains just enough for lib/Target/RISCV to compile. Notably a basic
RISCVTargetMachine and RISCVTargetInfo. At this point you can attempt llc
-march=riscv32 myinput.ll and will find it fails due to the lack of
MCAsmInfo.
See http://lists.llvm.org/pipermail/llvm-dev/2016-August/103748.html for
further discussion
Differential Revision: https://reviews.llvm.org/D23560
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285712 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'docs/CompilerWriterInfo.rst')
| -rw-r--r-- | docs/CompilerWriterInfo.rst | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/docs/CompilerWriterInfo.rst b/docs/CompilerWriterInfo.rst index 1aacb82ca67..a0c29976f4c 100644 --- a/docs/CompilerWriterInfo.rst +++ b/docs/CompilerWriterInfo.rst @@ -83,6 +83,10 @@ AMDGPU * `AMD Compute Resources <http://developer.amd.com/tools/heterogeneous-computing/amd-accelerated-parallel-processing-app-sdk/documentation/>`_ * `AMDGPU Compute Application Binary Interface <https://github.com/RadeonOpenCompute/ROCm-ComputeABI-Doc/blob/master/AMDGPU-ABI.md>`__ +RISC-V +------ +* `RISC-V User-Level ISA Specification <https://riscv.org/specifications/>`_ + SPARC ----- |