[CodeGen] Print live-out register lists as liveout(...) in both MIR and debug output

Work towards the unification of MIR and debug output by printing
`liveout(...)` instead of `<regliveout>`.

Only debug syntax is affected.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320683 91177308-0d34-0410-b5e6-96231b3b80d8

3 files changed, 37 insertions, 18 deletions

diff --git a/lib/CodeGen/MIRPrinter.cpp b/lib/CodeGen/MIRPrinter.cpp
index f625be36a81..fcf59adb7b3 100644
--- a/lib/CodeGen/MIRPrinter.cpp
+++ b/lib/CodeGen/MIRPrinter.cpp
@@ -797,7 +797,8 @@ void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx,
   case MachineOperand::MO_TargetIndex:
   case MachineOperand::MO_JumpTableIndex:
   case MachineOperand::MO_ExternalSymbol:
-  case MachineOperand::MO_GlobalAddress: {
+  case MachineOperand::MO_GlobalAddress:
+  case MachineOperand::MO_RegisterLiveOut: {
     unsigned TiedOperandIdx = 0;
     if (ShouldPrintRegisterTies && Op.isReg() && Op.isTied() && !Op.isDef())
       TiedOperandIdx = Op.getParent()->findTiedOperandIdx(OpIdx);
@@ -829,21 +830,6 @@ void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx,
       printCustomRegMask(Op.getRegMask(), OS, TRI);
     break;
   }
-  case MachineOperand::MO_RegisterLiveOut: {
-    const uint32_t *RegMask = Op.getRegLiveOut();
-    OS << "liveout(";
-    bool IsCommaNeeded = false;
-    for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
-      if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
-        if (IsCommaNeeded)
-          OS << ", ";
-        OS << printReg(Reg, TRI);
-        IsCommaNeeded = true;
-      }
-    }
-    OS << ")";
-    break;
-  }
   case MachineOperand::MO_Metadata:
     Op.getMetadata()->printAsOperand(OS, MST);
     break;
diff --git a/lib/CodeGen/MachineOperand.cpp b/lib/CodeGen/MachineOperand.cpp
index 7ffdbea08c1..009722b981a 100644
--- a/lib/CodeGen/MachineOperand.cpp
+++ b/lib/CodeGen/MachineOperand.cpp
@@ -637,9 +637,25 @@ void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
     OS << ">";
     break;
   }
-  case MachineOperand::MO_RegisterLiveOut:
-    OS << "<regliveout>";
+  case MachineOperand::MO_RegisterLiveOut: {
+    const uint32_t *RegMask = getRegLiveOut();
+    OS << "liveout(";
+    if (!TRI) {
+      OS << "<unknown>";
+    } else {
+      bool IsCommaNeeded = false;
+      for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
+        if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
+          if (IsCommaNeeded)
+            OS << ", ";
+          OS << printReg(Reg, TRI);
+          IsCommaNeeded = true;
+        }
+      }
+    }
+    OS << ")";
     break;
+  }
   case MachineOperand::MO_Metadata:
     OS << '<';
     getMetadata()->printAsOperand(OS, MST);
diff --git a/unittests/CodeGen/MachineOperandTest.cpp b/unittests/CodeGen/MachineOperandTest.cpp
index 96498e681ed..5c13ddc4b8c 100644
--- a/unittests/CodeGen/MachineOperandTest.cpp
+++ b/unittests/CodeGen/MachineOperandTest.cpp
@@ -272,4 +272,21 @@ TEST(MachineOperandTest, PrintGlobalAddress) {
   }
 }
 
+TEST(MachineOperandTest, PrintRegisterLiveOut) {
+  // Create a MachineOperand with a register live out list and print it.
+  uint32_t Mask = 0;
+  MachineOperand MO = MachineOperand::CreateRegLiveOut(&Mask);
+
+  // Checking some preconditions on the newly created
+  // MachineOperand.
+  ASSERT_TRUE(MO.isRegLiveOut());
+  ASSERT_TRUE(MO.getRegLiveOut() == &Mask);
+
+  std::string str;
+  // Print a MachineOperand containing a register live out list without a TRI.
+  raw_string_ostream OS(str);
+  MO.print(OS, /*TRI=*/nullptr, /*IntrinsicInfo=*/nullptr);
+  ASSERT_TRUE(OS.str() == "liveout(<unknown>)");
+}
+
 } // end namespace