add/move codegen tests for and/or of setcc; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299396 91177308-0d34-0410-b5e6-96231b3b80d8

5 files changed, 173 insertions, 73 deletions

diff --git a/test/CodeGen/ARM/and-setcc.ll b/test/CodeGen/ARM/and-setcc.ll
deleted file mode 100644
index 6dd6a446c7a..00000000000
--- a/test/CodeGen/ARM/and-setcc.ll
+++ /dev/null
@@ -1,36 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a8 | FileCheck %s
-
-define zeroext i1 @ne_neg1_and_ne_zero(i32 %x) nounwind {
-; CHECK-LABEL: ne_neg1_and_ne_zero:
-; CHECK:       @ BB#0:
-; CHECK-NEXT:    add r1, r0, #1
-; CHECK-NEXT:    mov r0, #0
-; CHECK-NEXT:    cmp r1, #1
-; CHECK-NEXT:    movwhi r0, #1
-; CHECK-NEXT:    bx lr
-  %cmp1 = icmp ne i32 %x, -1
-  %cmp2 = icmp ne i32 %x, 0
-  %and = and i1 %cmp1, %cmp2
-  ret i1 %and
-}
-
-; PR32401 - https://bugs.llvm.org/show_bug.cgi?id=32401
-
-define zeroext i1 @cmpeq_logical(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
-; CHECK-LABEL: cmpeq_logical:
-; CHECK:       @ BB#0:
-; CHECK-NEXT:    cmp r2, r3
-; CHECK-NEXT:    mov r2, #0
-; CHECK-NEXT:    movweq r2, #1
-; CHECK-NEXT:    mov r12, #0
-; CHECK-NEXT:    cmp r0, r1
-; CHECK-NEXT:    movweq r12, #1
-; CHECK-NEXT:    and r0, r12, r2
-; CHECK-NEXT:    bx lr
-  %cmp1 = icmp eq i32 %a, %b
-  %cmp2 = icmp eq i32 %c, %d
-  %and = and i1 %cmp1, %cmp2
-  ret i1 %and
-}
-
diff --git a/test/CodeGen/ARM/setcc-logic.ll b/test/CodeGen/ARM/setcc-logic.ll
new file mode 100644
index 00000000000..bfd188fb10d
--- /dev/null
+++ b/test/CodeGen/ARM/setcc-logic.ll
@@ -0,0 +1,79 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a8 | FileCheck %s
+
+define zeroext i1 @ne_neg1_and_ne_zero(i32 %x) nounwind {
+; CHECK-LABEL: ne_neg1_and_ne_zero:
+; CHECK:       @ BB#0:
+; CHECK-NEXT:    add r1, r0, #1
+; CHECK-NEXT:    mov r0, #0
+; CHECK-NEXT:    cmp r1, #1
+; CHECK-NEXT:    movwhi r0, #1
+; CHECK-NEXT:    bx lr
+  %cmp1 = icmp ne i32 %x, -1
+  %cmp2 = icmp ne i32 %x, 0
+  %and = and i1 %cmp1, %cmp2
+  ret i1 %and
+}
+
+; PR32401 - https://bugs.llvm.org/show_bug.cgi?id=32401
+
+define zeroext i1 @and_eq(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
+; CHECK-LABEL: and_eq:
+; CHECK:       @ BB#0:
+; CHECK-NEXT:    cmp r2, r3
+; CHECK-NEXT:    mov r2, #0
+; CHECK-NEXT:    movweq r2, #1
+; CHECK-NEXT:    mov r12, #0
+; CHECK-NEXT:    cmp r0, r1
+; CHECK-NEXT:    movweq r12, #1
+; CHECK-NEXT:    and r0, r12, r2
+; CHECK-NEXT:    bx lr
+  %cmp1 = icmp eq i32 %a, %b
+  %cmp2 = icmp eq i32 %c, %d
+  %and = and i1 %cmp1, %cmp2
+  ret i1 %and
+}
+
+define zeroext i1 @or_ne(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
+; CHECK-LABEL: or_ne:
+; CHECK:       @ BB#0:
+; CHECK-NEXT:    cmp r2, r3
+; CHECK-NEXT:    mov r2, #0
+; CHECK-NEXT:    movwne r2, #1
+; CHECK-NEXT:    mov r12, #0
+; CHECK-NEXT:    cmp r0, r1
+; CHECK-NEXT:    movwne r12, #1
+; CHECK-NEXT:    orr r0, r12, r2
+; CHECK-NEXT:    bx lr
+  %cmp1 = icmp ne i32 %a, %b
+  %cmp2 = icmp ne i32 %c, %d
+  %or = or i1 %cmp1, %cmp2
+  ret i1 %or
+}
+
+define <4 x i1> @and_eq_vec(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) nounwind {
+; CHECK-LABEL: and_eq_vec:
+; CHECK:       @ BB#0:
+; CHECK-NEXT:    .save {r11, lr}
+; CHECK-NEXT:    push {r11, lr}
+; CHECK-NEXT:    vmov d19, r2, r3
+; CHECK-NEXT:    add r12, sp, #40
+; CHECK-NEXT:    add lr, sp, #8
+; CHECK-NEXT:    vmov d18, r0, r1
+; CHECK-NEXT:    vld1.64 {d16, d17}, [lr]
+; CHECK-NEXT:    add r0, sp, #24
+; CHECK-NEXT:    vld1.64 {d20, d21}, [r12]
+; CHECK-NEXT:    vceq.i32 q8, q9, q8
+; CHECK-NEXT:    vld1.64 {d22, d23}, [r0]
+; CHECK-NEXT:    vceq.i32 q9, q11, q10
+; CHECK-NEXT:    vmovn.i32 d16, q8
+; CHECK-NEXT:    vmovn.i32 d17, q9
+; CHECK-NEXT:    vand d16, d16, d17
+; CHECK-NEXT:    vmov r0, r1, d16
+; CHECK-NEXT:    pop {r11, pc}
+  %cmp1 = icmp eq <4 x i32> %a, %b
+  %cmp2 = icmp eq <4 x i32> %c, %d
+  %and = and <4 x i1> %cmp1, %cmp2
+  ret <4 x i1> %and
+}
+
diff --git a/test/CodeGen/PowerPC/and-setcc.ll b/test/CodeGen/PowerPC/and-setcc.ll
deleted file mode 100644
index f7e25964d55..00000000000
--- a/test/CodeGen/PowerPC/and-setcc.ll
+++ /dev/null
@@ -1,35 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs | FileCheck %s
-
-define zeroext i1 @ne_neg1_and_ne_zero(i64 %x) {
-; CHECK-LABEL: ne_neg1_and_ne_zero:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    addi 3, 3, 1
-; CHECK-NEXT:    li 4, 0
-; CHECK-NEXT:    li 12, 1
-; CHECK-NEXT:    cmpldi 3, 1
-; CHECK-NEXT:    isel 3, 12, 4, 1
-; CHECK-NEXT:    blr
-  %cmp1 = icmp ne i64 %x, -1
-  %cmp2 = icmp ne i64 %x, 0
-  %and = and i1 %cmp1, %cmp2
-  ret i1 %and
-}
-
-; PR32401 - https://bugs.llvm.org/show_bug.cgi?id=32401
-
-define zeroext i1 @cmpeq_logical(i16 zeroext %a, i16 zeroext %b, i16 zeroext %c, i16 zeroext %d) {
-; CHECK-LABEL: cmpeq_logical:
-; CHECK:       # BB#0:
-; CHECK-NEXT:    cmpw 0, 3, 4
-; CHECK-NEXT:    cmpw 1, 5, 6
-; CHECK-NEXT:    li 3, 1
-; CHECK-NEXT:    crnand 20, 2, 6
-; CHECK-NEXT:    isel 3, 0, 3, 20
-; CHECK-NEXT:    blr
-  %cmp1 = icmp eq i16 %a, %b
-  %cmp2 = icmp eq i16 %c, %d
-  %and = and i1 %cmp1, %cmp2
-  ret i1 %and
-}
-
diff --git a/test/CodeGen/PowerPC/setcc-logic.ll b/test/CodeGen/PowerPC/setcc-logic.ll
index 6646c23947e..09cc1063ffd 100644
--- a/test/CodeGen/PowerPC/setcc-logic.ll
+++ b/test/CodeGen/PowerPC/setcc-logic.ll
@@ -413,3 +413,65 @@ define <4 x i1> @any_sign_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) {
   ret <4 x i1> %c
 }
 
+define zeroext i1 @ne_neg1_and_ne_zero(i64 %x) {
+; CHECK-LABEL: ne_neg1_and_ne_zero:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    addi 3, 3, 1
+; CHECK-NEXT:    li 4, 0
+; CHECK-NEXT:    li 12, 1
+; CHECK-NEXT:    cmpldi 3, 1
+; CHECK-NEXT:    isel 3, 12, 4, 1
+; CHECK-NEXT:    blr
+  %cmp1 = icmp ne i64 %x, -1
+  %cmp2 = icmp ne i64 %x, 0
+  %and = and i1 %cmp1, %cmp2
+  ret i1 %and
+}
+
+; PR32401 - https://bugs.llvm.org/show_bug.cgi?id=32401
+
+define zeroext i1 @and_eq(i16 zeroext  %a, i16 zeroext %b, i16 zeroext %c, i16 zeroext %d) {
+; CHECK-LABEL: and_eq:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    cmpw 0, 3, 4
+; CHECK-NEXT:    cmpw 1, 5, 6
+; CHECK-NEXT:    li 3, 1
+; CHECK-NEXT:    crnand 20, 2, 6
+; CHECK-NEXT:    isel 3, 0, 3, 20
+; CHECK-NEXT:    blr
+  %cmp1 = icmp eq i16 %a, %b
+  %cmp2 = icmp eq i16 %c, %d
+  %and = and i1 %cmp1, %cmp2
+  ret i1 %and
+}
+
+define zeroext i1 @or_ne(i32 %a, i32 %b, i32 %c, i32 %d) {
+; CHECK-LABEL: or_ne:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    cmpw 0, 3, 4
+; CHECK-NEXT:    cmpw 1, 5, 6
+; CHECK-NEXT:    li 3, 1
+; CHECK-NEXT:    crand 20, 6, 2
+; CHECK-NEXT:    isel 3, 0, 3, 20
+; CHECK-NEXT:    blr
+  %cmp1 = icmp ne i32 %a, %b
+  %cmp2 = icmp ne i32 %c, %d
+  %or = or i1 %cmp1, %cmp2
+  ret i1 %or
+}
+
+; This should not be transformed because vector compares + bitwise logic are faster.
+
+define <4 x i1> @and_eq_vec(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) {
+; CHECK-LABEL: and_eq_vec:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vcmpequw 2, 2, 3
+; CHECK-NEXT:    vcmpequw 19, 4, 5
+; CHECK-NEXT:    xxland 34, 34, 51
+; CHECK-NEXT:    blr
+  %cmp1 = icmp eq <4 x i32> %a, %b
+  %cmp2 = icmp eq <4 x i32> %c, %d
+  %and = and <4 x i1> %cmp1, %cmp2
+  ret <4 x i1> %and
+}
+
diff --git a/test/CodeGen/X86/setcc-logic.ll b/test/CodeGen/X86/setcc-logic.ll
index 2f0828cb0f5..8e6c149667c 100644
--- a/test/CodeGen/X86/setcc-logic.ll
+++ b/test/CodeGen/X86/setcc-logic.ll
@@ -437,8 +437,8 @@ define zeroext i1 @ne_neg1_and_ne_zero(i64 %x) nounwind {
 
 ; PR32401 - https://bugs.llvm.org/show_bug.cgi?id=32401
 
-define zeroext i1 @cmpeq_logical(i8 %a, i8 %b, i8 %c, i8 %d) nounwind {
-; CHECK-LABEL: cmpeq_logical:
+define zeroext i1 @and_eq(i8 %a, i8 %b, i8 %c, i8 %d) nounwind {
+; CHECK-LABEL: and_eq:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    cmpb %sil, %dil
 ; CHECK-NEXT:    sete %sil
@@ -452,3 +452,33 @@ define zeroext i1 @cmpeq_logical(i8 %a, i8 %b, i8 %c, i8 %d) nounwind {
   ret i1 %and
 }
 
+define zeroext i1 @or_ne(i8 %a, i8 %b, i8 %c, i8 %d) nounwind {
+; CHECK-LABEL: or_ne:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    cmpb %sil, %dil
+; CHECK-NEXT:    setne %sil
+; CHECK-NEXT:    cmpb %cl, %dl
+; CHECK-NEXT:    setne %al
+; CHECK-NEXT:    orb %sil, %al
+; CHECK-NEXT:    retq
+  %cmp1 = icmp ne i8 %a, %b
+  %cmp2 = icmp ne i8 %c, %d
+  %or = or i1 %cmp1, %cmp2
+  ret i1 %or
+}
+
+; This should not be transformed because vector compares + bitwise logic are faster.
+
+define <4 x i1> @and_eq_vec(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) nounwind {
+; CHECK-LABEL: and_eq_vec:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    pcmpeqd %xmm1, %xmm0
+; CHECK-NEXT:    pcmpeqd %xmm3, %xmm2
+; CHECK-NEXT:    pand %xmm2, %xmm0
+; CHECK-NEXT:    retq
+  %cmp1 = icmp eq <4 x i32> %a, %b
+  %cmp2 = icmp eq <4 x i32> %c, %d
+  %and = and <4 x i1> %cmp1, %cmp2
+  ret <4 x i1> %and
+}
+