[Hexagon] Add support for __builtin_prefetch

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261210 91177308-0d34-0410-b5e6-96231b3b80d8

6 files changed, 108 insertions, 0 deletions

diff --git a/lib/Target/Hexagon/HexagonISelLowering.cpp b/lib/Target/Hexagon/HexagonISelLowering.cpp
index 53492cb6b43..2a113118cf6 100644
--- a/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -990,6 +990,34 @@ HexagonTargetLowering::LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const {
   return Op;
 }
 
+// Need to transform ISD::PREFETCH into something that doesn't inherit
+// all of the properties of ISD::PREFETCH, specifically SDNPMayLoad and
+// SDNPMayStore.
+SDValue HexagonTargetLowering::LowerPREFETCH(SDValue Op,
+                                             SelectionDAG &DAG) const {
+  SDValue Chain = Op.getOperand(0);
+  SDValue Addr = Op.getOperand(1);
+  // Lower it to DCFETCH($reg, #0).  A "pat" will try to merge the offset in,
+  // if the "reg" is fed by an "add".
+  SDLoc DL(Op);
+  SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
+  return DAG.getNode(HexagonISD::DCFETCH, DL, MVT::Other, Chain, Addr, Zero);
+}
+
+SDValue HexagonTargetLowering::LowerINTRINSIC_VOID(SDValue Op,
+      SelectionDAG &DAG) const {
+  SDValue Chain = Op.getOperand(0);
+  unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
+  // Lower the hexagon_prefetch builtin to DCFETCH, as above.
+  if (IntNo == Intrinsic::hexagon_prefetch) {
+    SDValue Addr = Op.getOperand(2);
+    SDLoc DL(Op);
+    SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
+    return DAG.getNode(HexagonISD::DCFETCH, DL, MVT::Other, Chain, Addr, Zero);
+  }
+  return SDValue();
+}
+
 SDValue
 HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
                                                SelectionDAG &DAG) const {
@@ -1606,6 +1634,8 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
   setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
   setOperationAction(ISD::INLINEASM, MVT::Other, Custom);
+  setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
+  setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
   setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
   setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
   setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
@@ -2608,7 +2638,9 @@ HexagonTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
     case ISD::VSELECT:              return LowerVSELECT(Op, DAG);
     case ISD::CTPOP:                return LowerCTPOP(Op, DAG);
     case ISD::INTRINSIC_WO_CHAIN:   return LowerINTRINSIC_WO_CHAIN(Op, DAG);
+    case ISD::INTRINSIC_VOID:       return LowerINTRINSIC_VOID(Op, DAG);
     case ISD::INLINEASM:            return LowerINLINEASM(Op, DAG);
+    case ISD::PREFETCH:             return LowerPREFETCH(Op, DAG);
   }
 }
 
diff --git a/lib/Target/Hexagon/HexagonISelLowering.h b/lib/Target/Hexagon/HexagonISelLowering.h
index bf378b92222..1a682fcb9f3 100644
--- a/lib/Target/Hexagon/HexagonISelLowering.h
+++ b/lib/Target/Hexagon/HexagonISelLowering.h
@@ -128,6 +128,7 @@ bool isPositiveHalfWord(SDNode *N);
     SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
+    SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerEH_LABEL(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
@@ -207,6 +208,7 @@ bool isPositiveHalfWord(SDNode *N);
 
     // Intrinsics
     SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
+    SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
     /// isLegalAddressingMode - Return true if the addressing mode represented
     /// by AM is legal for this target, for a load/store of the specified type.
     /// The type may be VoidTy, in which case only return true if the addressing
diff --git a/lib/Target/Hexagon/HexagonInstrInfoV4.td b/lib/Target/Hexagon/HexagonInstrInfoV4.td
index f5dd943a2af..21bb258f7de 100644
--- a/lib/Target/Hexagon/HexagonInstrInfoV4.td
+++ b/lib/Target/Hexagon/HexagonInstrInfoV4.td
@@ -3996,6 +3996,10 @@ def Y2_dcfetchbo : LD0Inst<(outs), (ins IntRegs:$Rs, u11_3Imm:$u11_3),
   let Inst{10-0} = u11_3{13-3};
 }
 
+
+def: Pat<(HexagonDCFETCH (i32 (add IntRegs:$Rs, u11_3ImmPred:$u11_3)), (i32 0)),
+         (Y2_dcfetchbo IntRegs:$Rs, u11_3ImmPred:$u11_3)>;
+
 //===----------------------------------------------------------------------===//
 // Compound instructions
 //===----------------------------------------------------------------------===//
diff --git a/test/CodeGen/Hexagon/builtin-prefetch-offset.ll b/test/CodeGen/Hexagon/builtin-prefetch-offset.ll
new file mode 100644
index 00000000000..b542308abd3
--- /dev/null
+++ b/test/CodeGen/Hexagon/builtin-prefetch-offset.ll
@@ -0,0 +1,28 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; Check for the immediate offset.  It must be a multiple of 8.
+; CHECK: dcfetch({{.*}}+{{ *}}#8)
+; In 6.2 (which supports v4+ only), we generate indexed dcfetch in all cases
+; (unlike in 6.1, which supported v2, where dcfetch did not allow an immediate
+; offset).
+; For expression %2, where the offset is +9, the offset on dcfetch should be
+; a multiple of 8, and the offset of 0 is most likely (although not the only
+; possible one).  Check for #0 anyways, if the test fails with a false
+; positive, the second check can be eliminated, or rewritten, and in the
+; meantime it can help catch real problems.
+; CHECK: dcfetch({{.*}}+{{ *}}#0)
+target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
+target triple = "hexagon"
+
+define void @foo(i8* %addr) nounwind {
+entry:
+  %addr.addr = alloca i8*, align 4
+  store i8* %addr, i8** %addr.addr, align 4
+  %0 = load i8*, i8** %addr.addr, align 4
+  %1 = getelementptr i8, i8* %0, i32 8
+  call void @llvm.prefetch(i8* %1, i32 0, i32 3, i32 1)
+  %2 = getelementptr i8, i8* %0, i32 9
+  call void @llvm.prefetch(i8* %2, i32 0, i32 3, i32 1)
+  ret void
+}
+
+declare void @llvm.prefetch(i8* nocapture, i32, i32, i32) nounwind
diff --git a/test/CodeGen/Hexagon/builtin-prefetch.ll b/test/CodeGen/Hexagon/builtin-prefetch.ll
new file mode 100644
index 00000000000..ae236645b28
--- /dev/null
+++ b/test/CodeGen/Hexagon/builtin-prefetch.ll
@@ -0,0 +1,29 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; CHECK: dcfetch
+; CHECK: dcfetch{{.*}}#8
+target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
+target triple = "hexagon"
+
+; Function Attrs: nounwind
+define zeroext i8 @foo(i8* %addr) #0 {
+entry:
+  %addr.addr = alloca i8*, align 4
+  store i8* %addr, i8** %addr.addr, align 4
+  %0 = load i8*, i8** %addr.addr, align 4
+  call void @llvm.prefetch(i8* %0, i32 0, i32 3, i32 1)
+  %1 = load i8*, i8** %addr.addr, align 4
+  %2 = bitcast i8* %1 to i32*
+  %3 = load i32, i32* %2, align 4
+  %4 = add i32 %3, 8
+  %5 = inttoptr i32 %4 to i8*
+  call void @llvm.hexagon.prefetch(i8* %5)
+  %6 = load i8, i8* %5
+  ret i8 %6
+}
+
+; Function Attrs: nounwind
+declare void @llvm.prefetch(i8* nocapture, i32, i32, i32) #1
+declare void @llvm.hexagon.prefetch(i8* nocapture) #1
+
+attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { nounwind }
diff --git a/test/CodeGen/Hexagon/intrinsics/system_user.ll b/test/CodeGen/Hexagon/intrinsics/system_user.ll
new file mode 100644
index 00000000000..dad4effb0a1
--- /dev/null
+++ b/test/CodeGen/Hexagon/intrinsics/system_user.ll
@@ -0,0 +1,13 @@
+; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
+; RUN: llc -march=hexagon -O0 < %s | FileCheck -check-prefix=CHECK-CALL %s
+; Hexagon Programmer's Reference Manual 11.9.1 SYSTEM/USER
+
+; CHECK-CALL-NOT: call
+
+; Data cache prefetch
+declare void @llvm.hexagon.prefetch(i8*)
+define void @prefetch(i8* %a) {
+  call void @llvm.hexagon.prefetch(i8* %a)
+  ret void
+}
+; CHECK: dcfetch({{.*}} + #0)