diff options
| author | Reed Kotler <rkotler@mips.com> | 2013-10-08 17:32:33 +0000 |
|---|---|---|
| committer | Reed Kotler <rkotler@mips.com> | 2013-10-08 17:32:33 +0000 |
| commit | b359bda93d410623bbbc96dc9968d94447169a79 (patch) | |
| tree | 45a3f3958c647f75dab897bc55e4a7f646cb4946 | |
| parent | eb59e4d5ac15604643540b3aa1e5628d2d440dfc (diff) | |
Let rotr and bswap be handled by expansion for Mips16 since we don't
have native instructions for this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192207 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/Mips/Mips16ISelLowering.cpp | 5 | ||||
| -rw-r--r-- | test/CodeGen/Mips/bswap.ll | 3 | ||||
| -rw-r--r-- | test/CodeGen/Mips/rotate.ll | 5 |
3 files changed, 13 insertions, 0 deletions
diff --git a/lib/Target/Mips/Mips16ISelLowering.cpp b/lib/Target/Mips/Mips16ISelLowering.cpp index ab649bd9882..f0faca6d63c 100644 --- a/lib/Target/Mips/Mips16ISelLowering.cpp +++ b/lib/Target/Mips/Mips16ISelLowering.cpp @@ -145,6 +145,11 @@ Mips16TargetLowering::Mips16TargetLowering(MipsTargetMachine &TM) setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand); setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand); + setOperationAction(ISD::ROTR, MVT::i32, Expand); + setOperationAction(ISD::ROTR, MVT::i64, Expand); + setOperationAction(ISD::BSWAP, MVT::i32, Expand); + setOperationAction(ISD::BSWAP, MVT::i64, Expand); + computeRegisterProperties(); } diff --git a/test/CodeGen/Mips/bswap.ll b/test/CodeGen/Mips/bswap.ll index 0da2d2b7c28..f17b91aab80 100644 --- a/test/CodeGen/Mips/bswap.ll +++ b/test/CodeGen/Mips/bswap.ll @@ -1,11 +1,13 @@ ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=MIPS32 ; RUN: llc < %s -march=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefix=MIPS64 +; RUN: llc < %s -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips32r2 -mattr=+mips16 -soft-float -mips16-hard-float | FileCheck %s -check-prefix=mips16 define i32 @bswap32(i32 %x) nounwind readnone { entry: ; MIPS32-LABEL: bswap32: ; MIPS32: wsbh $[[R0:[0-9]+]] ; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16 +; mips16: .ent bswap32 %or.3 = call i32 @llvm.bswap.i32(i32 %x) ret i32 %or.3 } @@ -15,6 +17,7 @@ entry: ; MIPS64-LABEL: bswap64: ; MIPS64: dsbh $[[R0:[0-9]+]] ; MIPS64: dshd ${{[0-9]+}}, $[[R0]] +; mips16: .ent bswap64 %or.7 = call i64 @llvm.bswap.i64(i64 %x) ret i64 %or.7 } diff --git a/test/CodeGen/Mips/rotate.ll b/test/CodeGen/Mips/rotate.ll index 4f3cfb7df41..813bbdf18bb 100644 --- a/test/CodeGen/Mips/rotate.ll +++ b/test/CodeGen/Mips/rotate.ll @@ -1,6 +1,8 @@ ; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips32r2 -mattr=+mips16 -soft-float -mips16-hard-float < %s | FileCheck %s -check-prefix=mips16 ; CHECK: rotrv $2, $4 +; mips16: .ent rot0 define i32 @rot0(i32 %a, i32 %b) nounwind readnone { entry: %shl = shl i32 %a, %b @@ -11,6 +13,7 @@ entry: } ; CHECK: rotr $2, $4, 22 +; mips16: .ent rot1 define i32 @rot1(i32 %a) nounwind readnone { entry: %shl = shl i32 %a, 10 @@ -20,6 +23,7 @@ entry: } ; CHECK: rotrv $2, $4, $5 +; mips16: .ent rot2 define i32 @rot2(i32 %a, i32 %b) nounwind readnone { entry: %shr = lshr i32 %a, %b @@ -30,6 +34,7 @@ entry: } ; CHECK: rotr $2, $4, 10 +; mips16: .ent rot3 define i32 @rot3(i32 %a) nounwind readnone { entry: %shr = lshr i32 %a, 10 |