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| author | Hal Finkel <hfinkel@anl.gov> | 2015-02-06 23:30:06 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2015-02-06 23:30:06 +0000 |
| commit | 9ce4011708d5d8d90d9d0eaae572316f73d6366f (patch) | |
| tree | 29b9c789cabe26725846781dc5f9bfb11ecc4d66 | |
| parent | 2db85d688d87ecd0ab6812ee8343fb15ec7d22fe (diff) | |
[PowerPC] Fixup incomplete revert of test/CodeGen/PowerPC/tls-pic.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228467 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | test/CodeGen/PowerPC/tls-pic.ll | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/test/CodeGen/PowerPC/tls-pic.ll b/test/CodeGen/PowerPC/tls-pic.ll index 51e428a8866..9ba372591e6 100644 --- a/test/CodeGen/PowerPC/tls-pic.ll +++ b/test/CodeGen/PowerPC/tls-pic.ll @@ -19,32 +19,32 @@ entry: ; OPT0-LABEL: main: ; OPT0: addis [[REG:[0-9]+]], 2, a@got@tlsld@ha -; OPT0: addi 3, [[REG]], a@got@tlsld@l +; OPT0-NEXT: addi 3, [[REG]], a@got@tlsld@l ; OPT0: bl __tls_get_addr(a@tlsld) ; OPT0-NEXT: nop ; OPT0: addis [[REG2:[0-9]+]], 3, a@dtprel@ha -; OPT0: addi {{[0-9]+}}, [[REG2]], a@dtprel@l +; OPT0-NEXT: addi {{[0-9]+}}, [[REG2]], a@dtprel@l ; OPT0-32-LABEL: main -; OPT0-32: addi 3, {{[0-9]+}}, a@got@tlsld +; OPT0-32: addi {{[0-9]+}}, {{[0-9]+}}, a@got@tlsld ; OPT0-32: bl __tls_get_addr(a@tlsld)@PLT ; OPT0-32: addis [[REG:[0-9]+]], 3, a@dtprel@ha -; OPT0-32: addi {{[0-9]+}}, [[REG]], a@dtprel@l +; OPT0-32-NEXT: addi {{[0-9]+}}, [[REG]], a@dtprel@l ; OPT1-32-LABEL: main ; OPT1-32: addi 3, {{[0-9]+}}, a@got@tlsld ; OPT1-32: bl __tls_get_addr(a@tlsld)@PLT ; OPT1-32: addis [[REG:[0-9]+]], 3, a@dtprel@ha -; OPT1-32: addi {{[0-9]+}}, [[REG]], a@dtprel@l +; OPT1-32-NEXT: addi {{[0-9]+}}, [[REG]], a@dtprel@l ; Test peephole optimization for thread-local storage using the ; local dynamic model. ; OPT1-LABEL: main: ; OPT1: addis [[REG:[0-9]+]], 2, a@got@tlsld@ha -; OPT1: addi 3, [[REG]], a@got@tlsld@l +; OPT1-NEXT: addi 3, [[REG]], a@got@tlsld@l ; OPT1: bl __tls_get_addr(a@tlsld) ; OPT1-NEXT: nop ; OPT1: addis [[REG2:[0-9]+]], 3, a@dtprel@ha -; OPT1: lwa {{[0-9]+}}, a@dtprel@l([[REG2]]) +; OPT1-NEXT: lwa {{[0-9]+}}, a@dtprel@l([[REG2]]) ; Test correct assembly code generation for thread-local storage using ; the general dynamic model. |