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authorMatthias Braun <matze@braunis.de>2018-01-10 22:36:28 +0000
committerMatthias Braun <matze@braunis.de>2018-01-10 22:36:28 +0000
commit682df3f9a23ba3178f374aaeb2a05b06f23536ef (patch)
tree7c795d799bab1b0d522782bac1ee95f30eee84fa
parentd5651588f19c89ef437486387e8e4677684e78f8 (diff)
Revert "AArch64: Fix emergency spillslot being out of reach for large callframes"
Revert for now as the testcase is hitting a pre-existing verifier error that manifest as a failure when expensive checks are enabled (or -verify-machineinstrs) is used. This reverts commit r322200. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322231 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--include/llvm/CodeGen/TargetSubtargetInfo.h3
-rw-r--r--lib/CodeGen/MIRParser/MIRParser.cpp2
-rw-r--r--lib/CodeGen/TargetSubtargetInfo.cpp3
-rw-r--r--lib/Target/AArch64/AArch64FrameLowering.cpp32
-rw-r--r--lib/Target/AArch64/AArch64ISelLowering.cpp5
-rw-r--r--lib/Target/AArch64/AArch64ISelLowering.h2
-rw-r--r--lib/Target/AArch64/AArch64RegisterInfo.cpp12
-rw-r--r--lib/Target/AArch64/AArch64Subtarget.cpp10
-rw-r--r--lib/Target/AArch64/AArch64Subtarget.h2
-rw-r--r--test/CodeGen/AArch64/big-callframe.ll15
10 files changed, 11 insertions, 75 deletions
diff --git a/include/llvm/CodeGen/TargetSubtargetInfo.h b/include/llvm/CodeGen/TargetSubtargetInfo.h
index d5b413c5342..576522aef46 100644
--- a/include/llvm/CodeGen/TargetSubtargetInfo.h
+++ b/include/llvm/CodeGen/TargetSubtargetInfo.h
@@ -248,9 +248,6 @@ public:
/// Returns string representation of scheduler comment
std::string getSchedInfoStr(const MachineInstr &MI) const override;
std::string getSchedInfoStr(MCInst const &MCI) const override;
-
- /// This is called after a .mir file was loaded.
- virtual void mirFileLoaded(MachineFunction &MF) const;
};
} // end namespace llvm
diff --git a/lib/CodeGen/MIRParser/MIRParser.cpp b/lib/CodeGen/MIRParser/MIRParser.cpp
index e4e3fbbd75d..7d8e62736a3 100644
--- a/lib/CodeGen/MIRParser/MIRParser.cpp
+++ b/lib/CodeGen/MIRParser/MIRParser.cpp
@@ -417,8 +417,6 @@ MIRParserImpl::initializeMachineFunction(const yaml::MachineFunction &YamlMF,
computeFunctionProperties(MF);
- MF.getSubtarget().mirFileLoaded(MF);
-
MF.verify();
return false;
}
diff --git a/lib/CodeGen/TargetSubtargetInfo.cpp b/lib/CodeGen/TargetSubtargetInfo.cpp
index 7aab869f025..1a317cd865f 100644
--- a/lib/CodeGen/TargetSubtargetInfo.cpp
+++ b/lib/CodeGen/TargetSubtargetInfo.cpp
@@ -111,6 +111,3 @@ std::string TargetSubtargetInfo::getSchedInfoStr(MCInst const &MCI) const {
TSchedModel.computeInstrRThroughput(MCI.getOpcode());
return createSchedInfoStr(Latency, RThroughput);
}
-
-void TargetSubtargetInfo::mirFileLoaded(MachineFunction &MF) const {
-}
diff --git a/lib/Target/AArch64/AArch64FrameLowering.cpp b/lib/Target/AArch64/AArch64FrameLowering.cpp
index ea4bfe7e8d9..d66f7b59a4b 100644
--- a/lib/Target/AArch64/AArch64FrameLowering.cpp
+++ b/lib/Target/AArch64/AArch64FrameLowering.cpp
@@ -142,12 +142,6 @@ static cl::opt<bool> EnableRedZone("aarch64-redzone",
STATISTIC(NumRedZoneFunctions, "Number of functions using red zone");
-/// This is the biggest offset to the stack pointer we can encode in aarch64
-/// instructions (without using a separate calculation and a temp register).
-/// Note that the exception here are vector stores/loads which cannot encode any
-/// displacements (see estimateRSStackSizeLimit(), isAArch64FrameOffsetLegal()).
-static const unsigned DefaultSafeSPDisplacement = 255;
-
/// Look at each instruction that references stack frames and return the stack
/// size limit beyond which some of these instructions will require a scratch
/// register during their expansion later.
@@ -173,7 +167,7 @@ static unsigned estimateRSStackSizeLimit(MachineFunction &MF) {
}
}
}
- return DefaultSafeSPDisplacement;
+ return 255;
}
bool AArch64FrameLowering::canUseRedZone(const MachineFunction &MF) const {
@@ -197,25 +191,11 @@ bool AArch64FrameLowering::hasFP(const MachineFunction &MF) const {
const MachineFrameInfo &MFI = MF.getFrameInfo();
const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
// Retain behavior of always omitting the FP for leaf functions when possible.
- if (MFI.hasCalls() && MF.getTarget().Options.DisableFramePointerElim(MF))
- return true;
- if (MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken() ||
- MFI.hasStackMap() || MFI.hasPatchPoint() ||
- RegInfo->needsStackRealignment(MF))
- return true;
- // With large callframes around we may need to use FP to access the scavenging
- // emergency spillslot.
- //
- // Unfortunately some calls to hasFP() like machine verifier ->
- // getReservedReg() -> hasFP in the middle of global isel are too early
- // to know the max call frame size. Hopefully conservatively returning "true"
- // in those cases is fine.
- // DefaultSafeSPDisplacement is fine as we only emergency spill GP regs.
- if (!MFI.isMaxCallFrameSizeComputed() ||
- MFI.getMaxCallFrameSize() > DefaultSafeSPDisplacement)
- return true;
-
- return false;
+ return (MFI.hasCalls() &&
+ MF.getTarget().Options.DisableFramePointerElim(MF)) ||
+ MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken() ||
+ MFI.hasStackMap() || MFI.hasPatchPoint() ||
+ RegInfo->needsStackRealignment(MF);
}
/// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
diff --git a/lib/Target/AArch64/AArch64ISelLowering.cpp b/lib/Target/AArch64/AArch64ISelLowering.cpp
index c810fd777bd..41ed24c329e 100644
--- a/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -10974,8 +10974,3 @@ AArch64TargetLowering::getVaListSizeInBits(const DataLayout &DL) const {
return 3 * getPointerTy(DL).getSizeInBits() + 2 * 32;
}
-
-void AArch64TargetLowering::finalizeLowering(MachineFunction &MF) const {
- MF.getFrameInfo().computeMaxCallFrameSize(MF);
- TargetLoweringBase::finalizeLowering(MF);
-}
diff --git a/lib/Target/AArch64/AArch64ISelLowering.h b/lib/Target/AArch64/AArch64ISelLowering.h
index 6a89f23cdc8..8d78b5b6b5b 100644
--- a/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/lib/Target/AArch64/AArch64ISelLowering.h
@@ -647,8 +647,6 @@ private:
SelectionDAG &DAG) const override;
bool shouldNormalizeToSelectSequence(LLVMContext &, EVT) const override;
-
- void finalizeLowering(MachineFunction &MF) const override;
};
namespace AArch64 {
diff --git a/lib/Target/AArch64/AArch64RegisterInfo.cpp b/lib/Target/AArch64/AArch64RegisterInfo.cpp
index 360b39125b7..88dd297e007 100644
--- a/lib/Target/AArch64/AArch64RegisterInfo.cpp
+++ b/lib/Target/AArch64/AArch64RegisterInfo.cpp
@@ -225,13 +225,11 @@ bool AArch64RegisterInfo::requiresVirtualBaseRegisters(
bool
AArch64RegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {
- // This function indicates whether the emergency spillslot should be placed
- // close to the beginning of the stackframe (closer to FP) or the end
- // (closer to SP).
- //
- // The beginning works most reliably if we have a frame pointer.
- const AArch64FrameLowering &TFI = *getFrameLowering(MF);
- return TFI.hasFP(MF);
+ const MachineFrameInfo &MFI = MF.getFrameInfo();
+ // AArch64FrameLowering::resolveFrameIndexReference() can always fall back
+ // to the stack pointer, so only put the emergency spill slot next to the
+ // FP when there's no better way to access it (SP or base pointer).
+ return MFI.hasVarSizedObjects() && !hasBasePointer(MF);
}
bool AArch64RegisterInfo::requiresFrameIndexScavenging(
diff --git a/lib/Target/AArch64/AArch64Subtarget.cpp b/lib/Target/AArch64/AArch64Subtarget.cpp
index eb9bb1498d6..688bb936d0c 100644
--- a/lib/Target/AArch64/AArch64Subtarget.cpp
+++ b/lib/Target/AArch64/AArch64Subtarget.cpp
@@ -250,13 +250,3 @@ std::unique_ptr<PBQPRAConstraint>
AArch64Subtarget::getCustomPBQPConstraints() const {
return balanceFPOps() ? llvm::make_unique<A57ChainingConstraint>() : nullptr;
}
-
-void AArch64Subtarget::mirFileLoaded(MachineFunction &MF) const {
- // We usually compute max call frame size after ISel. Do the computation now
- // if the .mir file didn't specify it. Note that this will probably give you
- // bogus values after PEI has eliminated the callframe setup/destroy pseudo
- // instructions, specify explicitely if you need it to be correct.
- MachineFrameInfo &MFI = MF.getFrameInfo();
- if (!MFI.isMaxCallFrameSizeComputed())
- MFI.computeMaxCallFrameSize(MF);
-}
diff --git a/lib/Target/AArch64/AArch64Subtarget.h b/lib/Target/AArch64/AArch64Subtarget.h
index 45a8eb16464..9245b2f396b 100644
--- a/lib/Target/AArch64/AArch64Subtarget.h
+++ b/lib/Target/AArch64/AArch64Subtarget.h
@@ -326,8 +326,6 @@ public:
return false;
}
}
-
- void mirFileLoaded(MachineFunction &MF) const override;
};
} // End llvm namespace
diff --git a/test/CodeGen/AArch64/big-callframe.ll b/test/CodeGen/AArch64/big-callframe.ll
deleted file mode 100644
index 6c84e7f550e..00000000000
--- a/test/CodeGen/AArch64/big-callframe.ll
+++ /dev/null
@@ -1,15 +0,0 @@
-; RUN: llc -o - %s | FileCheck %s
-; Make sure we use a frame pointer and fp relative addressing for the emergency
-; spillslot when we have gigantic callframes.
-; CHECK-LABEL: func:
-; CHECK: stur {{.*}}, [x29, #{{.*}}] // 8-byte Folded Spill
-; CHECK: ldur {{.*}}, [x29, #{{.*}}] // 8-byte Folded Reload
-target triple = "aarch64--"
-declare void @extfunc([4096 x i64]* byval %p)
-define void @func([4096 x i64]* %z) {
- %lvar = alloca [31 x i8]
- %v = load volatile [31 x i8], [31 x i8]* %lvar
- store volatile [31 x i8] %v, [31 x i8]* %lvar
- call void @extfunc([4096 x i64]* byval %z)
- ret void
-}