[CodeGen] Print global addresses as @foo in both MIR and debug output

Work towards the unification of MIR and debug output by printing
`@foo` instead of `<ga:@foo>`.

Also print target flags in the MIR format since most of them are used on
global address operands.

Only debug syntax is affected.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320682 91177308-0d34-0410-b5e6-96231b3b80d8

11 files changed, 172 insertions, 136 deletions

diff --git a/include/llvm/CodeGen/MachineOperand.h b/include/llvm/CodeGen/MachineOperand.h
index c235649c009..a4c84be02e4 100644
--- a/include/llvm/CodeGen/MachineOperand.h
+++ b/include/llvm/CodeGen/MachineOperand.h
@@ -239,6 +239,8 @@ public:
   /// called to check this.
   static void printSubregIdx(raw_ostream &OS, uint64_t Index,
                              const TargetRegisterInfo *TRI);
+  /// Print operand target flags.
+  static void printTargetFlags(raw_ostream& OS, const MachineOperand &Op);
 
   /// Print the MachineOperand to \p os.
   /// Providing a valid \p TRI and \p IntrinsicInfo results in a more
diff --git a/lib/CodeGen/MIRPrinter.cpp b/lib/CodeGen/MIRPrinter.cpp
index 053ab607976..f625be36a81 100644
--- a/lib/CodeGen/MIRPrinter.cpp
+++ b/lib/CodeGen/MIRPrinter.cpp
@@ -161,7 +161,6 @@ public:
   void printIRValueReference(const Value &V);
   void printStackObjectReference(int FrameIndex);
   void printOffset(int64_t Offset);
-  void printTargetFlags(const MachineOperand &Op);
   void print(const MachineInstr &MI, unsigned OpIdx,
              const TargetRegisterInfo *TRI, bool ShouldPrintRegisterTies,
              LLT TypeToPrint, bool PrintDef = true);
@@ -778,72 +777,15 @@ void MIPrinter::printOffset(int64_t Offset) {
   OS << " + " << Offset;
 }
 
-static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
-  auto Flags = TII->getSerializableDirectMachineOperandTargetFlags();
-  for (const auto &I : Flags) {
-    if (I.first == TF) {
-      return I.second;
-    }
-  }
-  return nullptr;
-}
-
-void MIPrinter::printTargetFlags(const MachineOperand &Op) {
-  if (!Op.getTargetFlags())
-    return;
-  const auto *TII = Op.getParent()->getMF()->getSubtarget().getInstrInfo();
-  assert(TII && "expected instruction info");
-  auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
-  OS << "target-flags(";
-  const bool HasDirectFlags = Flags.first;
-  const bool HasBitmaskFlags = Flags.second;
-  if (!HasDirectFlags && !HasBitmaskFlags) {
-    OS << "<unknown>) ";
-    return;
-  }
-  if (HasDirectFlags) {
-    if (const auto *Name = getTargetFlagName(TII, Flags.first))
-      OS << Name;
-    else
-      OS << "<unknown target flag>";
-  }
-  if (!HasBitmaskFlags) {
-    OS << ") ";
-    return;
-  }
-  bool IsCommaNeeded = HasDirectFlags;
-  unsigned BitMask = Flags.second;
-  auto BitMasks = TII->getSerializableBitmaskMachineOperandTargetFlags();
-  for (const auto &Mask : BitMasks) {
-    // Check if the flag's bitmask has the bits of the current mask set.
-    if ((BitMask & Mask.first) == Mask.first) {
-      if (IsCommaNeeded)
-        OS << ", ";
-      IsCommaNeeded = true;
-      OS << Mask.second;
-      // Clear the bits which were serialized from the flag's bitmask.
-      BitMask &= ~(Mask.first);
-    }
-  }
-  if (BitMask) {
-    // When the resulting flag's bitmask isn't zero, we know that we didn't
-    // serialize all of the bit flags.
-    if (IsCommaNeeded)
-      OS << ", ";
-    OS << "<unknown bitmask target flag>";
-  }
-  OS << ") ";
-}
-
 void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx,
                       const TargetRegisterInfo *TRI,
                       bool ShouldPrintRegisterTies, LLT TypeToPrint,
                       bool PrintDef) {
   const MachineOperand &Op = MI.getOperand(OpIdx);
-  printTargetFlags(Op);
   switch (Op.getType()) {
   case MachineOperand::MO_Immediate:
     if (MI.isOperandSubregIdx(OpIdx)) {
+      MachineOperand::printTargetFlags(OS, Op);
       MachineOperand::printSubregIdx(OS, Op.getImm(), TRI);
       break;
     }
@@ -854,7 +796,8 @@ void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx,
   case MachineOperand::MO_ConstantPoolIndex:
   case MachineOperand::MO_TargetIndex:
   case MachineOperand::MO_JumpTableIndex:
-  case MachineOperand::MO_ExternalSymbol: {
+  case MachineOperand::MO_ExternalSymbol:
+  case MachineOperand::MO_GlobalAddress: {
     unsigned TiedOperandIdx = 0;
     if (ShouldPrintRegisterTies && Op.isReg() && Op.isTied() && !Op.isDef())
       TiedOperandIdx = Op.getParent()->findTiedOperandIdx(OpIdx);
@@ -869,10 +812,6 @@ void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx,
   case MachineOperand::MO_FrameIndex:
     printStackObjectReference(Op.getIndex());
     break;
-  case MachineOperand::MO_GlobalAddress:
-    Op.getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
-    printOffset(Op.getOffset());
-    break;
   case MachineOperand::MO_BlockAddress:
     OS << "blockaddress(";
     Op.getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
diff --git a/lib/CodeGen/MachineOperand.cpp b/lib/CodeGen/MachineOperand.cpp
index 6882e9ff700..7ffdbea08c1 100644
--- a/lib/CodeGen/MachineOperand.cpp
+++ b/lib/CodeGen/MachineOperand.cpp
@@ -401,6 +401,16 @@ static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
   return nullptr;
 }
 
+static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
+  auto Flags = TII->getSerializableDirectMachineOperandTargetFlags();
+  for (const auto &I : Flags) {
+    if (I.first == TF) {
+      return I.second;
+    }
+  }
+  return nullptr;
+}
+
 void MachineOperand::printSubregIdx(raw_ostream &OS, uint64_t Index,
                                     const TargetRegisterInfo *TRI) {
   OS << "%subreg.";
@@ -410,6 +420,58 @@ void MachineOperand::printSubregIdx(raw_ostream &OS, uint64_t Index,
     OS << Index;
 }
 
+void MachineOperand::printTargetFlags(raw_ostream &OS,
+                                      const MachineOperand &Op) {
+  if (!Op.getTargetFlags())
+    return;
+  const MachineFunction *MF = getMFIfAvailable(Op);
+  if (!MF)
+    return;
+
+  const auto *TII = MF->getSubtarget().getInstrInfo();
+  assert(TII && "expected instruction info");
+  auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
+  OS << "target-flags(";
+  const bool HasDirectFlags = Flags.first;
+  const bool HasBitmaskFlags = Flags.second;
+  if (!HasDirectFlags && !HasBitmaskFlags) {
+    OS << "<unknown>) ";
+    return;
+  }
+  if (HasDirectFlags) {
+    if (const auto *Name = getTargetFlagName(TII, Flags.first))
+      OS << Name;
+    else
+      OS << "<unknown target flag>";
+  }
+  if (!HasBitmaskFlags) {
+    OS << ") ";
+    return;
+  }
+  bool IsCommaNeeded = HasDirectFlags;
+  unsigned BitMask = Flags.second;
+  auto BitMasks = TII->getSerializableBitmaskMachineOperandTargetFlags();
+  for (const auto &Mask : BitMasks) {
+    // Check if the flag's bitmask has the bits of the current mask set.
+    if ((BitMask & Mask.first) == Mask.first) {
+      if (IsCommaNeeded)
+        OS << ", ";
+      IsCommaNeeded = true;
+      OS << Mask.second;
+      // Clear the bits which were serialized from the flag's bitmask.
+      BitMask &= ~(Mask.first);
+    }
+  }
+  if (BitMask) {
+    // When the resulting flag's bitmask isn't zero, we know that we didn't
+    // serialize all of the bit flags.
+    if (IsCommaNeeded)
+      OS << ", ";
+    OS << "<unknown bitmask target flag>";
+  }
+  OS << ") ";
+}
+
 void MachineOperand::print(raw_ostream &OS, const TargetRegisterInfo *TRI,
                            const TargetIntrinsicInfo *IntrinsicInfo) const {
   tryToGetTargetInfo(*this, TRI, IntrinsicInfo);
@@ -425,6 +487,7 @@ void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
                            unsigned TiedOperandIdx,
                            const TargetRegisterInfo *TRI,
                            const TargetIntrinsicInfo *IntrinsicInfo) const {
+  printTargetFlags(OS, *this);
   switch (getType()) {
   case MachineOperand::MO_Register: {
     unsigned Reg = getReg();
@@ -528,11 +591,8 @@ void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
     OS << printJumpTableEntryReference(getIndex());
     break;
   case MachineOperand::MO_GlobalAddress:
-    OS << "<ga:";
     getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
-    if (getOffset())
-      OS << "+" << getOffset();
-    OS << '>';
+    printOffset(OS, getOffset());
     break;
   case MachineOperand::MO_ExternalSymbol: {
     StringRef Name = getSymbolName();
@@ -608,8 +668,6 @@ void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
     break;
   }
   }
-  if (unsigned TF = getTargetFlags())
-    OS << "[TF=" << TF << ']';
 }
 
 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 02bf7739e15..a92a9165f27 100644
--- a/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -2882,7 +2882,7 @@ bool ARMBaseInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
   if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm)
     return false;
   if (!DefMI.getOperand(1).isImm())
-    // Could be t2MOVi32imm <ga:xx>
+    // Could be t2MOVi32imm @xx
     return false;
 
   if (!MRI->hasOneNonDBGUse(Reg))
diff --git a/lib/Target/PowerPC/PPCAsmPrinter.cpp b/lib/Target/PowerPC/PPCAsmPrinter.cpp
index 855406330b9..545f0aa0c2f 100644
--- a/lib/Target/PowerPC/PPCAsmPrinter.cpp
+++ b/lib/Target/PowerPC/PPCAsmPrinter.cpp
@@ -592,7 +592,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) {
     return;
   }
   case PPC::LWZtoc: {
-    // Transform %r3 = LWZtoc <ga:@min1>, %r2
+    // Transform %r3 = LWZtoc @min1, %r2
     LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin);
 
     // Change the opcode to LWZ, and the global address operand to be a
@@ -636,7 +636,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) {
   case PPC::LDtocCPT:
   case PPC::LDtocBA:
   case PPC::LDtoc: {
-    // Transform %x3 = LDtoc <ga:@min1>, %x2
+    // Transform %x3 = LDtoc @min1, %x2
     LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin);
 
     // Change the opcode to LD, and the global address operand to be a
@@ -667,7 +667,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) {
   }
 
   case PPC::ADDIStocHA: {
-    // Transform %xd = ADDIStocHA %x2, <ga:@sym>
+    // Transform %xd = ADDIStocHA %x2, @sym
     LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin);
 
     // Change the opcode to ADDIS8.  If the global address is external, has
@@ -714,7 +714,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) {
     return;
   }
   case PPC::LDtocL: {
-    // Transform %xd = LDtocL <ga:@sym>, %xs
+    // Transform %xd = LDtocL @sym, %xs
     LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin);
 
     // Change the opcode to LD.  If the global address is external, has
@@ -757,7 +757,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) {
     return;
   }
   case PPC::ADDItocL: {
-    // Transform %xd = ADDItocL %xs, <ga:@sym>
+    // Transform %xd = ADDItocL %xs, @sym
     LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin);
 
     // Change the opcode to ADDI8.  If the global address is external, then
@@ -788,7 +788,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) {
     return;
   }
   case PPC::ADDISgotTprelHA: {
-    // Transform: %xd = ADDISgotTprelHA %x2, <ga:@sym>
+    // Transform: %xd = ADDISgotTprelHA %x2, @sym
     // Into:      %xd = ADDIS8 %x2, sym@got@tlsgd@ha
     assert(Subtarget->isPPC64() && "Not supported for 32-bit PowerPC");
     const MachineOperand &MO = MI->getOperand(2);
@@ -805,7 +805,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) {
   }
   case PPC::LDgotTprelL:
   case PPC::LDgotTprelL32: {
-    // Transform %xd = LDgotTprelL <ga:@sym>, %xs
+    // Transform %xd = LDgotTprelL @sym, %xs
     LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin);
 
     // Change the opcode to LD.
@@ -866,7 +866,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) {
     return;
   }
   case PPC::ADDIStlsgdHA: {
-    // Transform: %xd = ADDIStlsgdHA %x2, <ga:@sym>
+    // Transform: %xd = ADDIStlsgdHA %x2, @sym
     // Into:      %xd = ADDIS8 %x2, sym@got@tlsgd@ha
     assert(Subtarget->isPPC64() && "Not supported for 32-bit PowerPC");
     const MachineOperand &MO = MI->getOperand(2);
@@ -882,10 +882,10 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) {
     return;
   }
   case PPC::ADDItlsgdL:
-    // Transform: %xd = ADDItlsgdL %xs, <ga:@sym>
+    // Transform: %xd = ADDItlsgdL %xs, @sym
     // Into:      %xd = ADDI8 %xs, sym@got@tlsgd@l
   case PPC::ADDItlsgdL32: {
-    // Transform: %rd = ADDItlsgdL32 %rs, <ga:@sym>
+    // Transform: %rd = ADDItlsgdL32 %rs, @sym
     // Into:      %rd = ADDI %rs, sym@got@tlsgd
     const MachineOperand &MO = MI->getOperand(2);
     const GlobalValue *GValue = MO.getGlobal();
@@ -902,16 +902,16 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) {
     return;
   }
   case PPC::GETtlsADDR:
-    // Transform: %x3 = GETtlsADDR %x3, <ga:@sym>
+    // Transform: %x3 = GETtlsADDR %x3, @sym
     // Into: BL8_NOP_TLS __tls_get_addr(sym at tlsgd)
   case PPC::GETtlsADDR32: {
-    // Transform: %r3 = GETtlsADDR32 %r3, <ga:@sym>
+    // Transform: %r3 = GETtlsADDR32 %r3, @sym
     // Into: BL_TLS __tls_get_addr(sym at tlsgd)@PLT
     EmitTlsCall(MI, MCSymbolRefExpr::VK_PPC_TLSGD);
     return;
   }
   case PPC::ADDIStlsldHA: {
-    // Transform: %xd = ADDIStlsldHA %x2, <ga:@sym>
+    // Transform: %xd = ADDIStlsldHA %x2, @sym
     // Into:      %xd = ADDIS8 %x2, sym@got@tlsld@ha
     assert(Subtarget->isPPC64() && "Not supported for 32-bit PowerPC");
     const MachineOperand &MO = MI->getOperand(2);
@@ -927,10 +927,10 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) {
     return;
   }
   case PPC::ADDItlsldL:
-    // Transform: %xd = ADDItlsldL %xs, <ga:@sym>
+    // Transform: %xd = ADDItlsldL %xs, @sym
     // Into:      %xd = ADDI8 %xs, sym@got@tlsld@l
   case PPC::ADDItlsldL32: {
-    // Transform: %rd = ADDItlsldL32 %rs, <ga:@sym>
+    // Transform: %rd = ADDItlsldL32 %rs, @sym
     // Into:      %rd = ADDI %rs, sym@got@tlsld
     const MachineOperand &MO = MI->getOperand(2);
     const GlobalValue *GValue = MO.getGlobal();
@@ -947,19 +947,19 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) {
     return;
   }
   case PPC::GETtlsldADDR:
-    // Transform: %x3 = GETtlsldADDR %x3, <ga:@sym>
+    // Transform: %x3 = GETtlsldADDR %x3, @sym
     // Into: BL8_NOP_TLS __tls_get_addr(sym at tlsld)
   case PPC::GETtlsldADDR32: {
-    // Transform: %r3 = GETtlsldADDR32 %r3, <ga:@sym>
+    // Transform: %r3 = GETtlsldADDR32 %r3, @sym
     // Into: BL_TLS __tls_get_addr(sym at tlsld)@PLT
     EmitTlsCall(MI, MCSymbolRefExpr::VK_PPC_TLSLD);
     return;
   }
   case PPC::ADDISdtprelHA:
-    // Transform: %xd = ADDISdtprelHA %xs, <ga:@sym>
+    // Transform: %xd = ADDISdtprelHA %xs, @sym
     // Into:      %xd = ADDIS8 %xs, sym@dtprel@ha
   case PPC::ADDISdtprelHA32: {
-    // Transform: %rd = ADDISdtprelHA32 %rs, <ga:@sym>
+    // Transform: %rd = ADDISdtprelHA32 %rs, @sym
     // Into:      %rd = ADDIS %rs, sym@dtprel@ha
     const MachineOperand &MO = MI->getOperand(2);
     const GlobalValue *GValue = MO.getGlobal();
@@ -976,10 +976,10 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) {
     return;
   }
   case PPC::ADDIdtprelL:
-    // Transform: %xd = ADDIdtprelL %xs, <ga:@sym>
+    // Transform: %xd = ADDIdtprelL %xs, @sym
     // Into:      %xd = ADDI8 %xs, sym@dtprel@l
   case PPC::ADDIdtprelL32: {
-    // Transform: %rd = ADDIdtprelL32 %rs, <ga:@sym>
+    // Transform: %rd = ADDIdtprelL32 %rs, @sym
     // Into:      %rd = ADDI %rs, sym@dtprel@l
     const MachineOperand &MO = MI->getOperand(2);
     const GlobalValue *GValue = MO.getGlobal();
diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index a9ef10bc600..cf5c3e8b5c6 100644
--- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -4518,9 +4518,9 @@ void PPCDAGToDAGISel::Select(SDNode *N) {
 
     // The first source operand is a TargetGlobalAddress or a TargetJumpTable.
     // If it must be toc-referenced according to PPCSubTarget, we generate:
-    //   LDtocL(<ga:@sym>, ADDIStocHA(%x2, <ga:@sym>))
+    //   LDtocL(@sym, ADDIStocHA(%x2, @sym))
     // Otherwise we generate:
-    //   ADDItocL(ADDIStocHA(%x2, <ga:@sym>), <ga:@sym>)
+    //   ADDItocL(ADDIStocHA(%x2, @sym), @sym)
     SDValue GA = N->getOperand(0);
     SDValue TOCbase = N->getOperand(1);
     SDNode *Tmp = CurDAG->getMachineNode(PPC::ADDIStocHA, dl, MVT::i64,
diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp
index 1eb798ce5bf..15e457543a9 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -2316,7 +2316,7 @@ PPCInstrInfo::isSignOrZeroExtended(const MachineInstr &MI, bool SignExt,
       // For a method return value, we check the ZExt/SExt flags in attribute.
       // We assume the following code sequence for method call.
       //   ADJCALLSTACKDOWN 32, implicit dead %r1, implicit %r1
-      //   BL8_NOP <ga:@func>,...
+      //   BL8_NOP @func,...
       //   ADJCALLSTACKUP 32, 0, implicit dead %r1, implicit %r1
       //   %5 = COPY %x3; G8RC:%5
       if (SrcReg == PPC::X3) {
diff --git a/test/CodeGen/AArch64/loh.mir b/test/CodeGen/AArch64/loh.mir
index 1e42ecfd599..ee62c339cf0 100644
--- a/test/CodeGen/AArch64/loh.mir
+++ b/test/CodeGen/AArch64/loh.mir
@@ -22,14 +22,14 @@ tracksRegLiveness: true
 body: |
   bb.0:
     ; CHECK: Adding MCLOH_AdrpAdrp:
-    ; CHECK-NEXT: %x1 = ADRP <ga:@g3>
-    ; CHECK-NEXT: %x1 = ADRP <ga:@g4>
+    ; CHECK-NEXT: %x1 = ADRP target-flags(aarch64-page) @g3
+    ; CHECK-NEXT: %x1 = ADRP target-flags(aarch64-page) @g4
     ; CHECK-NEXT: Adding MCLOH_AdrpAdrp:
-    ; CHECK-NEXT: %x1 = ADRP <ga:@g2>
-    ; CHECK-NEXT: %x1 = ADRP <ga:@g3>
+    ; CHECK-NEXT: %x1 = ADRP target-flags(aarch64-page) @g2
+    ; CHECK-NEXT: %x1 = ADRP target-flags(aarch64-page) @g3
     ; CHECK-NEXT: Adding MCLOH_AdrpAdrp:
-    ; CHECK-NEXT: %x0 = ADRP <ga:@g0>
-    ; CHECK-NEXT: %x0 = ADRP <ga:@g1>
+    ; CHECK-NEXT: %x0 = ADRP target-flags(aarch64-page) @g0
+    ; CHECK-NEXT: %x0 = ADRP target-flags(aarch64-page) @g1
     %x0 = ADRP target-flags(aarch64-page) @g0
     %x0 = ADRP target-flags(aarch64-page) @g1
     %x1 = ADRP target-flags(aarch64-page) @g2
@@ -38,11 +38,11 @@ body: |
 
   bb.1:
     ; CHECK-NEXT: Adding MCLOH_AdrpAdd:
-    ; CHECK-NEXT: %x20 = ADRP <ga:@g0>
-    ; CHECK-NEXT: %x3 = ADDXri %x20, <ga:@g0>
+    ; CHECK-NEXT: %x20 = ADRP target-flags(aarch64-page) @g0
+    ; CHECK-NEXT: %x3 = ADDXri %x20, target-flags(aarch64-pageoff) @g0
     ; CHECK-NEXT: Adding MCLOH_AdrpAdd:
-    ; CHECK-NEXT: %x1 = ADRP <ga:@g0>
-    ; CHECK-NEXT: %x1 = ADDXri %x1, <ga:@g0>
+    ; CHECK-NEXT: %x1 = ADRP target-flags(aarch64-page) @g0
+    ; CHECK-NEXT: %x1 = ADDXri %x1, target-flags(aarch64-pageoff) @g0
     %x1 = ADRP target-flags(aarch64-page) @g0
     %x9 = SUBXri undef %x11, 5, 0 ; should not affect MCLOH formation
     %x1 = ADDXri %x1, target-flags(aarch64-pageoff) @g0, 0
@@ -73,11 +73,11 @@ body: |
 
   bb.5:
     ; CHECK-NEXT: Adding MCLOH_AdrpLdr:
-    ; CHECK-NEXT: %x5 = ADRP <ga:@g2>
-    ; CHECK-NEXT: %s6 = LDRSui %x5, <ga:@g2>
+    ; CHECK-NEXT: %x5 = ADRP target-flags(aarch64-page) @g2
+    ; CHECK-NEXT: %s6 = LDRSui %x5, target-flags(aarch64-pageoff) @g2
     ; CHECK-NEXT: Adding MCLOH_AdrpLdr:
-    ; CHECK-NEXT: %x4 = ADRP <ga:@g2>
-    ; CHECK-NEXT: %x4 = LDRXui %x4, <ga:@g2>
+    ; CHECK-NEXT: %x4 = ADRP target-flags(aarch64-page) @g2
+    ; CHECK-NEXT: %x4 = LDRXui %x4, target-flags(aarch64-pageoff) @g2
     %x4 = ADRP target-flags(aarch64-page) @g2
     %x4 = LDRXui %x4, target-flags(aarch64-pageoff) @g2
     %x5 = ADRP target-flags(aarch64-page) @g2
@@ -85,11 +85,11 @@ body: |
 
   bb.6:
     ; CHECK-NEXT: Adding MCLOH_AdrpLdrGot:
-    ; CHECK-NEXT: %x5 = ADRP <ga:@g2>
-    ; CHECK-NEXT: %x6 = LDRXui %x5, <ga:@g2>
+    ; CHECK-NEXT: %x5 = ADRP target-flags(aarch64-page, aarch64-got) @g2
+    ; CHECK-NEXT: %x6 = LDRXui %x5, target-flags(aarch64-pageoff, aarch64-got) @g2
     ; CHECK-NEXT: Adding MCLOH_AdrpLdrGot:
-    ; CHECK-NEXT: %x4 = ADRP <ga:@g2>
-    ; CHECK-NEXT: %x4 = LDRXui %x4, <ga:@g2>
+    ; CHECK-NEXT: %x4 = ADRP target-flags(aarch64-page, aarch64-got) @g2
+    ; CHECK-NEXT: %x4 = LDRXui %x4, target-flags(aarch64-pageoff, aarch64-got) @g2
     %x4 = ADRP target-flags(aarch64-page, aarch64-got) @g2
     %x4 = LDRXui %x4, target-flags(aarch64-pageoff, aarch64-got) @g2
     %x5 = ADRP target-flags(aarch64-page, aarch64-got) @g2
@@ -104,8 +104,8 @@ body: |
 
   bb.8:
     ; CHECK-NEXT: Adding MCLOH_AdrpAddLdr:
-    ; CHECK-NEXT: %x7 = ADRP <ga:@g3>[TF=1]
-    ; CHECK-NEXT: %x8 = ADDXri %x7, <ga:@g3>
+    ; CHECK-NEXT: %x7 = ADRP target-flags(aarch64-page) @g3
+    ; CHECK-NEXT: %x8 = ADDXri %x7, target-flags(aarch64-pageoff) @g3
     ; CHECK-NEXT: %d1 = LDRDui %x8, 8
     %x7 = ADRP target-flags(aarch64-page) @g3
     %x8 = ADDXri %x7, target-flags(aarch64-pageoff) @g3, 0
@@ -113,14 +113,14 @@ body: |
 
   bb.9:
     ; CHECK-NEXT: Adding MCLOH_AdrpAdd:
-    ; CHECK-NEXT: %x3 = ADRP <ga:@g3>
-    ; CHECK-NEXT: %x3 = ADDXri %x3, <ga:@g3>
+    ; CHECK-NEXT: %x3 = ADRP target-flags(aarch64-page) @g3
+    ; CHECK-NEXT: %x3 = ADDXri %x3, target-flags(aarch64-pageoff) @g3
     ; CHECK-NEXT: Adding MCLOH_AdrpAdd:
-    ; CHECK-NEXT: %x5 = ADRP <ga:@g3>
-    ; CHECK-NEXT: %x2 = ADDXri %x5, <ga:@g3>
+    ; CHECK-NEXT: %x5 = ADRP target-flags(aarch64-page) @g3
+    ; CHECK-NEXT: %x2 = ADDXri %x5, target-flags(aarch64-pageoff) @g3
     ; CHECK-NEXT: Adding MCLOH_AdrpAddStr:
-    ; CHECK-NEXT: %x1 = ADRP <ga:@g3>
-    ; CHECK-NEXT: %x1 = ADDXri %x1, <ga:@g3>
+    ; CHECK-NEXT: %x1 = ADRP target-flags(aarch64-page) @g3
+    ; CHECK-NEXT: %x1 = ADDXri %x1, target-flags(aarch64-pageoff) @g3
     ; CHECK-NEXT: STRXui %xzr, %x1, 16
     %x1 = ADRP target-flags(aarch64-page) @g3
     %x1 = ADDXri %x1, target-flags(aarch64-pageoff) @g3, 0
@@ -138,11 +138,11 @@ body: |
 
   bb.10:
     ; CHECK-NEXT: Adding MCLOH_AdrpLdr:
-    ; CHECK-NEXT: %x2 = ADRP <ga:@g3>
-    ; CHECK-NEXT: %x2 = LDRXui %x2, <ga:@g3>
+    ; CHECK-NEXT: %x2 = ADRP target-flags(aarch64-page) @g3
+    ; CHECK-NEXT: %x2 = LDRXui %x2, target-flags(aarch64-pageoff) @g3
     ; CHECK-NEXT: Adding MCLOH_AdrpLdrGotLdr:
-    ; CHECK-NEXT: %x1 = ADRP <ga:@g4>
-    ; CHECK-NEXT: %x1 = LDRXui %x1, <ga:@g4>
+    ; CHECK-NEXT: %x1 = ADRP target-flags(aarch64-page, aarch64-got) @g4
+    ; CHECK-NEXT: %x1 = LDRXui %x1, target-flags(aarch64-pageoff, aarch64-got) @g4
     ; CHECK-NEXT: %x1 = LDRXui %x1, 24
     %x1 = ADRP target-flags(aarch64-page, aarch64-got) @g4
     %x1 = LDRXui %x1, target-flags(aarch64-pageoff, aarch64-got) @g4
@@ -154,11 +154,11 @@ body: |
 
   bb.11:
     ; CHECK-NEXT: Adding MCLOH_AdrpLdr
-    ; CHECK-NEXT: %x5 = ADRP <ga:@g1>
-    ; CHECK-NEXT: %x5 = LDRXui %x5, <ga:@g1>
+    ; CHECK-NEXT: %x5 = ADRP target-flags(aarch64-page) @g1
+    ; CHECK-NEXT: %x5 = LDRXui %x5, target-flags(aarch64-pageoff) @g1
     ; CHECK-NEXT: Adding MCLOH_AdrpLdrGotStr:
-    ; CHECK-NEXT: %x1 = ADRP <ga:@g4>
-    ; CHECK-NEXT: %x1 = LDRXui %x1, <ga:@g4>
+    ; CHECK-NEXT: %x1 = ADRP target-flags(aarch64-page, aarch64-got) @g4
+    ; CHECK-NEXT: %x1 = LDRXui %x1, target-flags(aarch64-pageoff, aarch64-got) @g4
     ; CHECK-NEXT: STRXui %xzr, %x1, 32
     %x1 = ADRP target-flags(aarch64-page, aarch64-got) @g4
     %x1 = LDRXui %x1, target-flags(aarch64-pageoff, aarch64-got) @g4
@@ -171,8 +171,8 @@ body: |
   bb.12:
     ; CHECK-NOT: MCLOH_AdrpAdrp
     ; CHECK: Adding MCLOH_AdrpAddLdr
-    ; %x9 = ADRP <ga:@g4>
-    ; %x9 = ADDXri %x9, <ga:@g4>
+    ; %x9 = ADRP @g4
+    ; %x9 = ADDXri %x9, @g4
     ; %x5 = LDRXui %x9, 0
     %x9 = ADRP target-flags(aarch64-page, aarch64-got) @g4
     %x9 = ADDXri %x9, target-flags(aarch64-pageoff, aarch64-got) @g4, 0
diff --git a/test/CodeGen/ARM/misched-int-basic-thumb2.mir b/test/CodeGen/ARM/misched-int-basic-thumb2.mir
index 6f813d4f860..ace3aa3bde6 100644
--- a/test/CodeGen/ARM/misched-int-basic-thumb2.mir
+++ b/test/CodeGen/ARM/misched-int-basic-thumb2.mir
@@ -37,7 +37,7 @@
   }
 #
 # CHECK:       ********** MI Scheduling **********
-# CHECK:       SU(2):   %2:rgpr = t2MOVi32imm <ga:@g1>; rGPR:%2
+# CHECK:       SU(2):   %2:rgpr = t2MOVi32imm @g1; rGPR:%2
 # CHECK_A9:    Latency    : 2
 # CHECK_SWIFT: Latency    : 2
 # CHECK_R52:   Latency    : 2
diff --git a/test/CodeGen/X86/stack-protector-weight.ll b/test/CodeGen/X86/stack-protector-weight.ll
index 74050195277..e8a4746bb64 100644
--- a/test/CodeGen/X86/stack-protector-weight.ll
+++ b/test/CodeGen/X86/stack-protector-weight.ll
@@ -13,20 +13,20 @@
 ; DARWIN-IR: Successors according to CFG: %bb.[[SUCCESS:[0-9]+]]({{[0-9a-fx/= ]+}}100.00%) %bb.[[FAILURE:[0-9]+]]
 ; DARWIN-IR: %bb.[[SUCCESS]]:
 ; DARWIN-IR: %bb.[[FAILURE]]:
-; DARWIN-IR: CALL64pcrel32 <ga:@__stack_chk_fail>
+; DARWIN-IR: CALL64pcrel32 @__stack_chk_fail
 
 ; MSVC-SELDAG: # Machine code for function test_branch_weights:
 ; MSVC-SELDAG: mem:Volatile LD4[@__security_cookie]
 ; MSVC-SELDAG: ST4[FixedStack0]
 ; MSVC-SELDAG: LD4[FixedStack0]
-; MSVC-SELDAG: CALLpcrel32 <ga:@__security_check_cookie>
+; MSVC-SELDAG: CALLpcrel32 @__security_check_cookie
 
 ; MSVC always uses selection DAG now.
 ; MSVC-IR: # Machine code for function test_branch_weights:
 ; MSVC-IR: mem:Volatile LD4[@__security_cookie]
 ; MSVC-IR: ST4[FixedStack0]
 ; MSVC-IR: LD4[FixedStack0]
-; MSVC-IR: CALLpcrel32 <ga:@__security_check_cookie>
+; MSVC-IR: CALLpcrel32 @__security_check_cookie
 
 define i32 @test_branch_weights(i32 %n) #0 {
 entry:
diff --git a/unittests/CodeGen/MachineOperandTest.cpp b/unittests/CodeGen/MachineOperandTest.cpp
index 36897d918b3..96498e681ed 100644
--- a/unittests/CodeGen/MachineOperandTest.cpp
+++ b/unittests/CodeGen/MachineOperandTest.cpp
@@ -7,10 +7,11 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "llvm/ADT/ilist_node.h"
 #include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/ADT/ilist_node.h"
 #include "llvm/IR/Constants.h"
 #include "llvm/IR/LLVMContext.h"
+#include "llvm/IR/Module.h"
 #include "llvm/IR/ModuleSlotTracker.h"
 #include "llvm/Support/raw_ostream.h"
 #include "gtest/gtest.h"
@@ -235,4 +236,40 @@ TEST(MachineOperandTest, PrintExternalSymbol) {
   }
 }
 
+TEST(MachineOperandTest, PrintGlobalAddress) {
+  LLVMContext Ctx;
+  Module M("MachineOperandGVTest", Ctx);
+  M.getOrInsertGlobal("foo", Type::getInt32Ty(Ctx));
+
+  GlobalValue *GV = M.getNamedValue("foo");
+
+  // Create a MachineOperand with a global address and a positive offset and
+  // print it.
+  MachineOperand MO = MachineOperand::CreateGA(GV, 12);
+
+  // Checking some preconditions on the newly created
+  // MachineOperand.
+  ASSERT_TRUE(MO.isGlobal());
+  ASSERT_TRUE(MO.getGlobal() == GV);
+  ASSERT_TRUE(MO.getOffset() == 12);
+
+  std::string str;
+  // Print a MachineOperand containing a global address and a positive offset.
+  {
+    raw_string_ostream OS(str);
+    MO.print(OS, /*TRI=*/nullptr, /*IntrinsicInfo=*/nullptr);
+    ASSERT_TRUE(OS.str() == "@foo + 12");
+  }
+
+  str.clear();
+  MO.setOffset(-12);
+
+  // Print a MachineOperand containing a global address and a negative offset.
+  {
+    raw_string_ostream OS(str);
+    MO.print(OS, /*TRI=*/nullptr, /*IntrinsicInfo=*/nullptr);
+    ASSERT_TRUE(OS.str() == "@foo - 12");
+  }
+}
+
 } // end namespace