diff options
author | Zoran Jovanovic <zoran.jovanovic@imgtec.com> | 2014-03-31 14:00:10 +0000 |
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committer | Zoran Jovanovic <zoran.jovanovic@imgtec.com> | 2014-03-31 14:00:10 +0000 |
commit | 077aa54e4ef322b2cfbd99bbffde6416b8467820 (patch) | |
tree | 78eb6b66783e4b4255c95fd80217ee2c520ed303 | |
parent | 6889086ba11db4c82fef8efa86fdee5502d71156 (diff) |
Fixed issue with microMIPS JAL instruction.
Differential Revision: http://llvm-reviews.chandlerc.com/D3200
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205185 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/Mips/MicroMipsInstrInfo.td | 7 | ||||
-rw-r--r-- | lib/Target/Mips/MipsISelLowering.cpp | 5 | ||||
-rw-r--r-- | lib/Target/Mips/MipsISelLowering.h | 3 | ||||
-rw-r--r-- | lib/Target/Mips/MipsInstrInfo.td | 4 | ||||
-rw-r--r-- | test/CodeGen/Mips/micromips-jal.ll | 48 |
5 files changed, 52 insertions, 15 deletions
diff --git a/lib/Target/Mips/MicroMipsInstrInfo.td b/lib/Target/Mips/MicroMipsInstrInfo.td index 15be0593089..853734a7a94 100644 --- a/lib/Target/Mips/MicroMipsInstrInfo.td +++ b/lib/Target/Mips/MicroMipsInstrInfo.td @@ -78,15 +78,10 @@ class MoveMM16<string opstr, RegisterOperand RO, bit isComm = 0, let isReMaterializable = 1; } -// MicroMIPS Call -def MicroMipsJmpLink : SDNode<"MipsISD::JmpLinkMM",SDT_MipsJmpLink, - [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, - SDNPVariadic]>; - // 16-bit Jump and Link (Call) class JumpLinkRegMM16<string opstr, RegisterOperand RO> : MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), - [(MicroMipsJmpLink RO:$rs)], IIBranch, FrmR> { + [(MipsJmpLink RO:$rs)], IIBranch, FrmR> { let isCall = 1; let hasDelaySlot = 1; let Defs = [RA]; diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp index 11eee42946c..04520b7a221 100644 --- a/lib/Target/Mips/MipsISelLowering.cpp +++ b/lib/Target/Mips/MipsISelLowering.cpp @@ -115,7 +115,6 @@ SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty, const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { switch (Opcode) { case MipsISD::JmpLink: return "MipsISD::JmpLink"; - case MipsISD::JmpLinkMM: return "MipsISD::JmpLinkMM"; case MipsISD::TailCall: return "MipsISD::TailCall"; case MipsISD::Hi: return "MipsISD::Hi"; case MipsISD::Lo: return "MipsISD::Lo"; @@ -2546,9 +2545,7 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, if (IsTailCall) return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, &Ops[0], Ops.size()); - MipsISD::NodeType JmpLink = isMicroMips ? MipsISD::JmpLinkMM - : MipsISD::JmpLink; - Chain = DAG.getNode(JmpLink, DL, NodeTys, &Ops[0], Ops.size()); + Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, &Ops[0], Ops.size()); SDValue InFlag = Chain.getValue(1); // Create the CALLSEQ_END node. diff --git a/lib/Target/Mips/MipsISelLowering.h b/lib/Target/Mips/MipsISelLowering.h index 32759fbdd5a..5a105ffc893 100644 --- a/lib/Target/Mips/MipsISelLowering.h +++ b/lib/Target/Mips/MipsISelLowering.h @@ -34,9 +34,6 @@ namespace llvm { // Jump and link (call) JmpLink, - // MicroMIPS Jump and link (call) - JmpLinkMM, - // Tail call TailCall, diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 1584d296709..af4fa6410c8 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -1044,11 +1044,11 @@ def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>, def B : UncondBranch<BEQ>; def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>; -let Predicates = [NotInMicroMips] in { +let Predicates = [NotInMicroMips, HasStdEnc] in { def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM; +def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>; } def JALX : JumpLink<"jalx", calltarget>, FJ<0x1D>; -def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>; def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>; def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>; def BAL_BR : BAL_BR_Pseudo<BGEZAL>; diff --git a/test/CodeGen/Mips/micromips-jal.ll b/test/CodeGen/Mips/micromips-jal.ll new file mode 100644 index 00000000000..fccc2291972 --- /dev/null +++ b/test/CodeGen/Mips/micromips-jal.ll @@ -0,0 +1,48 @@ +; RUN: llc %s -march=mipsel -mcpu=mips32r2 -mattr=micromips -filetype=asm \ +; RUN: -relocation-model=static -o - | FileCheck %s + +define i32 @sum(i32 %a, i32 %b) nounwind uwtable { +entry: + %a.addr = alloca i32, align 4 + %b.addr = alloca i32, align 4 + store i32 %a, i32* %a.addr, align 4 + store i32 %b, i32* %b.addr, align 4 + %0 = load i32* %a.addr, align 4 + %1 = load i32* %b.addr, align 4 + %add = add nsw i32 %0, %1 + ret i32 %add +} + +define i32 @main() nounwind uwtable { +entry: + %retval = alloca i32, align 4 + %x = alloca i32, align 4 + %y = alloca i32, align 4 + %z = alloca i32, align 4 + store i32 0, i32* %retval + %0 = load i32* %y, align 4 + %1 = load i32* %z, align 4 + %call = call i32 @sum(i32 %0, i32 %1) + store i32 %call, i32* %x, align 4 + %2 = load i32* %x, align 4 + ret i32 %2 +} + +; CHECK: .text + +; CHECK: .globl sum +; CHECK: .type sum,@function +; CHECK: .set micromips +; CHECK: .ent sum +; CHECK-LABEL: sum: +; CHECK: .end sum + +; CHECK: .globl main +; CHECK: .type main,@function +; CHECK: .set micromips +; CHECK: .ent main +; CHECK-LABEL: main: + +; CHECK: jal sum + +; CHECK: .end main |