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| author | Hans Wennborg <hans@hanshq.net> | 2018-08-02 09:15:30 +0000 |
|---|---|---|
| committer | Hans Wennborg <hans@hanshq.net> | 2018-08-02 09:15:30 +0000 |
| commit | d030aee3d2d544dbecef32b2f0df28e2a384688a (patch) | |
| tree | 2a2cf906eb052f9c4b31a30666fb7501f8dee003 | |
| parent | 9dbe7c72d17465cdf311d9e43b02171c4117dcc7 (diff) | |
Merging r338554:
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r338554 | bryanpkc | 2018-08-01 15:50:29 +0200 (Wed, 01 Aug 2018) | 11 lines
[AArch64] Fix FCCMP with FP16 operands
Summary: This patch adds support for FCCMP instruction with FP16 operands, avoiding an assertion during instruction selection.
Reviewers: olista01, SjoerdMeijer, t.p.northover, javed.absar
Reviewed By: SjoerdMeijer
Subscribers: kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D50115
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_70@338692 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/AArch64/AArch64InstrFormats.td | 4 | ||||
| -rw-r--r-- | test/CodeGen/AArch64/f16-instructions.ll | 30 |
2 files changed, 33 insertions, 1 deletions
diff --git a/lib/Target/AArch64/AArch64InstrFormats.td b/lib/Target/AArch64/AArch64InstrFormats.td index 15d61cd1ad2..7caf32dbde2 100644 --- a/lib/Target/AArch64/AArch64InstrFormats.td +++ b/lib/Target/AArch64/AArch64InstrFormats.td @@ -4639,7 +4639,9 @@ class BaseFPCondComparison<bit signalAllNans, RegisterClass regtype, multiclass FPCondComparison<bit signalAllNans, string mnemonic, SDPatternOperator OpNode = null_frag> { - def Hrr : BaseFPCondComparison<signalAllNans, FPR16, mnemonic, []> { + def Hrr : BaseFPCondComparison<signalAllNans, FPR16, mnemonic, + [(set NZCV, (OpNode (f16 FPR16:$Rn), (f16 FPR16:$Rm), (i32 imm:$nzcv), + (i32 imm:$cond), NZCV))]> { let Inst{23-22} = 0b11; let Predicates = [HasFullFP16]; } diff --git a/test/CodeGen/AArch64/f16-instructions.ll b/test/CodeGen/AArch64/f16-instructions.ll index c6c279d7d21..352a2753903 100644 --- a/test/CodeGen/AArch64/f16-instructions.ll +++ b/test/CodeGen/AArch64/f16-instructions.ll @@ -456,6 +456,36 @@ define i1 @test_fcmp_ord(half %a, half %b) #0 { ret i1 %r } +; CHECK-COMMON-LABEL: test_fccmp: +; CHECK-CVT: fcvt s0, h0 +; CHECK-CVT-NEXT: fmov s1, #8.00000000 +; CHECK-CVT-NEXT: fmov s2, #5.00000000 +; CHECK-CVT-NEXT: fcmp s0, s1 +; CHECK-CVT-NEXT: cset w8, gt +; CHECK-CVT-NEXT: fcmp s0, s2 +; CHECK-CVT-NEXT: cset w9, mi +; CHECK-CVT-NEXT: tst w8, w9 +; CHECK-CVT-NEXT: fcsel s0, s0, s2, ne +; CHECK-CVT-NEXT: fcvt h0, s0 +; CHECK-CVT-NEXT: str h0, [x0] +; CHECK-CVT-NEXT: ret +; CHECK-FP16: fmov h1, #5.00000000 +; CHECK-FP16-NEXT: fcmp h0, h1 +; CHECK-FP16-NEXT: fmov h2, #8.00000000 +; CHECK-FP16-NEXT: fccmp h0, h2, #4, mi +; CHECK-FP16-NEXT: fcsel h0, h0, h1, gt +; CHECK-FP16-NEXT: str h0, [x0] +; CHECK-FP16-NEXT: ret + +define void @test_fccmp(half %in, half* %out) { + %cmp1 = fcmp ogt half %in, 0xH4800 + %cmp2 = fcmp olt half %in, 0xH4500 + %cond = and i1 %cmp1, %cmp2 + %result = select i1 %cond, half %in, half 0xH4500 + store half %result, half* %out + ret void +} + ; CHECK-CVT-LABEL: test_br_cc: ; CHECK-CVT-NEXT: fcvt s1, h1 ; CHECK-CVT-NEXT: fcvt s0, h0 |