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| author | Tom Stellard <tstellar@redhat.com> | 2018-11-13 05:43:07 +0000 |
|---|---|---|
| committer | Tom Stellard <tstellar@redhat.com> | 2018-11-13 05:43:07 +0000 |
| commit | 6ef29028d44462250fa7e99ed0627e73757d1777 (patch) | |
| tree | 8ff184472f0271459684826edd998d233985cc0f | |
| parent | b7cd010ff5e925f168e6eb7a2687e831073ea5b0 (diff) | |
Merging r341919:
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r341919 | atanasyan | 2018-09-11 02:57:25 -0700 (Tue, 11 Sep 2018) | 18 lines
[mips] Add a pattern for 64-bit GPR variant of the `rdhwr` instruction
MIPS ISAs start to support third operand for the `rdhwr` instruction
starting from Revision 6. But LLVM generates assembler code with
three-operands version of this instruction on any MIPS64 ISA. The third
operand is always zero, so in case of direct code generation we get
correct code.
This patch fixes the bug by adding an instruction alias. The same alias
already exists for 32-bit ISA.
Ideally, we also need to reject three-operands version of the `rdhwr`
instruction in an assembler code if ISA revision is less than 6. That is
a task for a separate patch.
This fixes PR38861 (https://bugs.llvm.org/show_bug.cgi?id=38861)
Differential revision: https://reviews.llvm.org/D51773
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_70@346739 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/Mips/Mips64InstrInfo.td | 3 | ||||
| -rw-r--r-- | test/CodeGen/Mips/tls.ll | 8 |
2 files changed, 7 insertions, 4 deletions
diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index 878ec29b188..fb6b4affacb 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -1139,3 +1139,6 @@ def SLTUImm64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rs), "sltu\t$rs, $rt, $imm">, GPR_64; def : MipsInstAlias<"sltu\t$rs, $imm", (SLTUImm64 GPR64Opnd:$rs, GPR64Opnd:$rs, imm64:$imm)>, GPR_64; + +def : MipsInstAlias<"rdhwr $rt, $rs", + (RDHWR64 GPR64Opnd:$rt, HWRegsOpnd:$rs, 0), 1>, GPR_64; diff --git a/test/CodeGen/Mips/tls.ll b/test/CodeGen/Mips/tls.ll index 3ef9d63196c..126cfea9728 100644 --- a/test/CodeGen/Mips/tls.ll +++ b/test/CodeGen/Mips/tls.ll @@ -48,14 +48,14 @@ entry: ; STATIC32-LABEL: f1: ; STATIC32: lui $[[R0:[0-9]+]], %tprel_hi(t1) ; STATIC32: addiu $[[R1:[0-9]+]], $[[R0]], %tprel_lo(t1) -; STATIC32: rdhwr $3, $29 +; STATIC32: rdhwr $3, $29{{$}} ; STATIC32: addu $[[R2:[0-9]+]], $3, $[[R1]] ; STATIC32: lw $2, 0($[[R2]]) ; STATIC64-LABEL: f1: ; STATIC64: lui $[[R0:[0-9]+]], %tprel_hi(t1) ; STATIC64: daddiu $[[R1:[0-9]+]], $[[R0]], %tprel_lo(t1) -; STATIC64: rdhwr $3, $29, 0 +; STATIC64: rdhwr $3, $29{{$}} ; STATIC64: daddu $[[R2:[0-9]+]], $3, $[[R0]] ; STATIC64: lw $2, 0($[[R2]]) } @@ -101,7 +101,7 @@ entry: ; STATIC32-LABEL: f2: ; STATIC32: lui $[[R0:[0-9]+]], %hi(__gnu_local_gp) ; STATIC32: addiu $[[GP:[0-9]+]], $[[R0]], %lo(__gnu_local_gp) -; STATIC32: rdhwr $3, $29 +; STATIC32: rdhwr $3, $29{{$}} ; STATIC32: lw $[[R0:[0-9]+]], %gottprel(t2)($[[GP]]) ; STATIC32: addu $[[R1:[0-9]+]], $3, $[[R0]] ; STATIC32: lw $2, 0($[[R1]]) @@ -109,7 +109,7 @@ entry: ; STATIC64-LABEL: f2: ; STATIC64: lui $[[R0:[0-9]+]], %hi(%neg(%gp_rel(f2))) ; STATIC64: daddiu $[[GP:[0-9]+]], $[[R0]], %lo(%neg(%gp_rel(f2))) -; STATIC64: rdhwr $3, $29 +; STATIC64: rdhwr $3, $29{{$}} ; STATIC64: ld $[[R0:[0-9]+]], %gottprel(t2)($[[GP]]) ; STATIC64: daddu $[[R1:[0-9]+]], $3, $[[R0]] ; STATIC64: lw $2, 0($[[R1]]) |