[7.0 branch] Update release notes (SystemZ, TableGen)

This updates the 7.0 branch release notes to mention the SystemZ
specific changes, and also the new support for multi-alternative
patterns in TableGen (see D48545).

Reviewed by: hans
Differential Revision: https://reviews.llvm.org/D50514



git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_70@339355 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 24 insertions, 0 deletions

diff --git a/docs/ReleaseNotes.rst b/docs/ReleaseNotes.rst
index 6f85cc4c5d5..2963a3df3a1 100644
--- a/docs/ReleaseNotes.rst
+++ b/docs/ReleaseNotes.rst
@@ -161,6 +161,26 @@ Changes to the PowerPC Target
 
  During this release ...
 
+Changes to the SystemZ Target
+-----------------------------
+
+During this release the SystemZ target has:
+
+* Added support for vector registers in inline asm statements.
+
+* Added support for stackmaps, patchpoints, and the anyregcc
+  calling convention.
+
+* Changed the default function alignment to 16 bytes.
+
+* Improved codegen for condition code handling.
+
+* Improved instruction scheduling and microarchitecture tuning for z13/z14.
+
+* Fixed support for generating GCOV coverage data.
+
+* Fixed some codegen bugs.
+
 Changes to the X86 Target
 -------------------------
 
@@ -198,6 +218,10 @@ Changes to the DAG infrastructure
 
 * The SETCCE opcode has now been removed in favor of SETCCCARRY.
 
+* TableGen now supports multi-alternative pattern fragments via the PatFrags
+  class.  PatFrag is now derived from PatFrags, which may require minor
+  changes to backends that directly access PatFrag members.
+
 External Open Source Projects Using LLVM 7
 ==========================================