[AArch64][GlobalISel] Fall back during AArch64 isel if we have a volatile load.

The tablegen imported patterns for sext(load(a)) don't check for single uses
of the load or delete the original after matching. As a result two loads are
left in the generated code. This particular issue will be fixed by adding
support for a G_SEXTLOAD opcode in future.

There are however other potential issues around this that wouldn't be fixed by
a G_SEXTLOAD, so until we have a proper solution we don't try to handle volatile
loads at all in the AArch64 selector.

Fixes/works around PR36018.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@323371 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 20 insertions, 0 deletions

diff --git a/lib/Target/AArch64/AArch64InstructionSelector.cpp b/lib/Target/AArch64/AArch64InstructionSelector.cpp
index 392ba13d74a..34d0483c403 100644
--- a/lib/Target/AArch64/AArch64InstructionSelector.cpp
+++ b/lib/Target/AArch64/AArch64InstructionSelector.cpp
@@ -931,6 +931,12 @@ bool AArch64InstructionSelector::select(MachineInstr &I,
       return false;
     }
 
+    // FIXME: PR36018: Volatile loads in some cases are incorrectly selected by
+    // folding with an extend. Until we have a G_SEXTLOAD solution bail out if
+    // we hit one.
+    if (Opcode == TargetOpcode::G_LOAD && MemOp.isVolatile())
+      return false;
+
     const unsigned PtrReg = I.getOperand(1).getReg();
 #ifndef NDEBUG
     const RegisterBank &PtrRB = *RBI.getRegBank(PtrReg, MRI, TRI);
diff --git a/test/CodeGen/AArch64/GlobalISel/irtranslator-volatile-load-pr36018.ll b/test/CodeGen/AArch64/GlobalISel/irtranslator-volatile-load-pr36018.ll
new file mode 100644
index 00000000000..9bda39c9fca
--- /dev/null
+++ b/test/CodeGen/AArch64/GlobalISel/irtranslator-volatile-load-pr36018.ll
@@ -0,0 +1,14 @@
+; RUN: llc -O0 -mtriple=aarch64-apple-ios -o - %s | FileCheck %s
+
+@g = global i16 0, align 2
+declare void @bar(i32)
+
+; Check that only one load is generated. We fall back to
+define hidden void @foo() {
+; CHECK-NOT: ldrh
+; CHECK: ldrsh
+  %1 = load volatile i16, i16* @g, align 2
+  %2 = sext i16 %1 to i32
+  call void @bar(i32 %2)
+  ret void
+}